mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 17:07:38 +00:00
5d7a95f499
Synchronise device trees with linux v5.19-rc5. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
182 lines
4.3 KiB
Text
182 lines
4.3 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016 PHYTEC Messtechnik GmbH
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* Author: Christian Hemp <c.hemp@phytec.de>
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pwm/pwm.h>
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/ {
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model = "PHYTEC phyCORE-i.MX6 UltraLite";
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compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
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chosen {
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stdout-path = &uart1;
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};
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/*
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* Set the minimum memory size here and
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* let the bootloader set the real size.
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*/
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x8000000>;
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};
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gpio_leds_som: leds {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpioleds_som>;
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compatible = "gpio-leds";
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phycore-green {
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gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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phy-mode = "rmii";
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phy-handle = <ðphy1>;
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status = "disabled";
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy1: ethernet-phy@1 {
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reg = <1>;
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interrupt-parent = <&gpio1>;
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interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
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micrel,led-mode = <1>;
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clocks = <&clks IMX6UL_CLK_ENET_REF>;
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clock-names = "rmii-ref";
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status = "disabled";
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};
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};
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand>;
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nand-on-flash-bbt;
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status = "disabled";
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};
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&i2c1 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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clock-frequency = <100000>;
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status = "okay";
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eeprom@52 {
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compatible = "catalyst,24c32", "atmel,24c32";
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pagesize = <32>;
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reg = <0x52>;
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};
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};
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&snvs_poweroff {
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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bus-width = <8>;
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no-1-8-v;
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non-removable;
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status = "disabled";
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};
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&iomuxc {
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x10010
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MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x10010
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MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
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MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010
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MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010
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MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010
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MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010
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MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x17059
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>;
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};
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pinctrl_gpioleds_som: gpioledssomgrp {
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fsl,pins = <MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0>;
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};
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pinctrl_gpmi_nand: gpminandgrp {
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fsl,pins = <
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MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
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MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
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MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
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MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
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MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
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MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
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MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
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MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
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MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
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MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
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MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
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MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
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MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
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MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
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MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
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>;
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};
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pinctrl_i2c1: i2cgrp {
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fsl,pins = <
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MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
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MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
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>;
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};
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pinctrl_i2c1_gpio: i2cgpiogrp {
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fsl,pins = <
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MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0
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MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
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MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
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MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
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MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
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MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
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MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
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MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
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MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
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MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
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MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
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MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
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>;
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};
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};
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