mirror of
https://github.com/AsahiLinux/u-boot
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256 lines
7.4 KiB
C
256 lines
7.4 KiB
C
/*
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* (C) Copyright 2001-2003
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* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <command.h>
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/* ------------------------------------------------------------------------- */
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#ifdef FPGA_DEBUG
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#define DBG(x...) printf(x)
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#else
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#define DBG(x...)
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#endif /* DEBUG */
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#define MAX_ONES 226
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#ifdef CONFIG_SYS_FPGA_PRG
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# define FPGA_PRG CONFIG_SYS_FPGA_PRG /* FPGA program pin (ppc output)*/
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# define FPGA_CLK CONFIG_SYS_FPGA_CLK /* FPGA clk pin (ppc output) */
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# define FPGA_DATA CONFIG_SYS_FPGA_DATA /* FPGA data pin (ppc output) */
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# define FPGA_DONE CONFIG_SYS_FPGA_DONE /* FPGA done pin (ppc input) */
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# define FPGA_INIT CONFIG_SYS_FPGA_INIT /* FPGA init pin (ppc input) */
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#else
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# define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
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# define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
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# define FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
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# define FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
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# define FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
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#endif
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#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */
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#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */
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#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */
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#define SET_FPGA(data) out32(GPIO0_OR, data)
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#define FPGA_WRITE_1 { \
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SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
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SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \
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SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \
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SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
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#define FPGA_WRITE_0 { \
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SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
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SET_FPGA(FPGA_PRG); /* set data to 0 */ \
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SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \
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SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
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#if 0
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static int fpga_boot (unsigned char *fpgadata, int size)
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{
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int i, index, len;
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int count;
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#ifdef CONFIG_SYS_FPGA_SPARTAN2
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int j;
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#else
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unsigned char b;
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int bit;
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#endif
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/* display infos on fpgaimage */
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index = 15;
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for (i = 0; i < 4; i++) {
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len = fpgadata[index];
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DBG ("FPGA: %s\n", &(fpgadata[index + 1]));
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index += len + 3;
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}
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#ifdef CONFIG_SYS_FPGA_SPARTAN2
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/* search for preamble 0xFFFFFFFF */
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while (1) {
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if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
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&& (fpgadata[index + 2] == 0xff)
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&& (fpgadata[index + 3] == 0xff))
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break; /* preamble found */
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else
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index++;
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}
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#else
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/* search for preamble 0xFF2X */
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for (index = 0; index < size - 1; index++) {
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if ((fpgadata[index] == 0xff)
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&& ((fpgadata[index + 1] & 0xf0) == 0x30))
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break;
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}
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index += 2;
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#endif
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DBG ("FPGA: configdata starts at position 0x%x\n", index);
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DBG ("FPGA: length of fpga-data %d\n", size - index);
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/*
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* Setup port pins for fpga programming
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*/
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out32 (GPIO0_ODR, 0x00000000); /* no open drain pins */
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out32 (GPIO0_TCR, in32 (GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */
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out32 (GPIO0_OR, in32 (GPIO0_OR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set pins to high */
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DBG ("%s, ",
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((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
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DBG ("%s\n",
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((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
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/*
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* Init fpga by asserting and deasserting PROGRAM*
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*/
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SET_FPGA (FPGA_CLK | FPGA_DATA);
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/* Wait for FPGA init line low */
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count = 0;
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while (in32 (GPIO0_IR) & FPGA_INIT) {
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udelay (1000); /* wait 1ms */
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/* Check for timeout - 100us max, so use 3ms */
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if (count++ > 3) {
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DBG ("FPGA: Booting failed!\n");
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return ERROR_FPGA_PRG_INIT_LOW;
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}
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}
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DBG ("%s, ",
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((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
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DBG ("%s\n",
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((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
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/* deassert PROGRAM* */
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SET_FPGA (FPGA_PRG | FPGA_CLK | FPGA_DATA);
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/* Wait for FPGA end of init period . */
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count = 0;
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while (!(in32 (GPIO0_IR) & FPGA_INIT)) {
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udelay (1000); /* wait 1ms */
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/* Check for timeout */
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if (count++ > 3) {
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DBG ("FPGA: Booting failed!\n");
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return ERROR_FPGA_PRG_INIT_HIGH;
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}
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}
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DBG ("%s, ",
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((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
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DBG ("%s\n",
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((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
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DBG ("write configuration data into fpga\n");
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/* write configuration-data into fpga... */
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#ifdef CONFIG_SYS_FPGA_SPARTAN2
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/*
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* Load uncompressed image into fpga
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*/
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for (i = index; i < size; i++) {
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for (j = 0; j < 8; j++) {
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if ((fpgadata[i] & 0x80) == 0x80) {
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FPGA_WRITE_1;
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} else {
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FPGA_WRITE_0;
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}
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fpgadata[i] <<= 1;
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}
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}
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#else /* ! CONFIG_SYS_FPGA_SPARTAN2 */
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/* send 0xff 0x20 */
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FPGA_WRITE_1;
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FPGA_WRITE_1;
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FPGA_WRITE_1;
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FPGA_WRITE_1;
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FPGA_WRITE_1;
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FPGA_WRITE_1;
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FPGA_WRITE_1;
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FPGA_WRITE_1;
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FPGA_WRITE_0;
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FPGA_WRITE_0;
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FPGA_WRITE_1;
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FPGA_WRITE_0;
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FPGA_WRITE_0;
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FPGA_WRITE_0;
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FPGA_WRITE_0;
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FPGA_WRITE_0;
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/*
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** Bit_DeCompression
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** Code 1 .. maxOnes : n '1's followed by '0'
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** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0'
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** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1'
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** 255 : '1'
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*/
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for (i = index; i < size; i++) {
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b = fpgadata[i];
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if ((b >= 1) && (b <= MAX_ONES)) {
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for (bit = 0; bit < b; bit++) {
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FPGA_WRITE_1;
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}
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FPGA_WRITE_0;
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} else if (b == (MAX_ONES + 1)) {
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for (bit = 1; bit < b; bit++) {
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FPGA_WRITE_1;
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}
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} else if ((b >= (MAX_ONES + 2)) && (b <= 254)) {
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for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) {
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FPGA_WRITE_0;
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}
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FPGA_WRITE_1;
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} else if (b == 255) {
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FPGA_WRITE_1;
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}
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}
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#endif /* CONFIG_SYS_FPGA_SPARTAN2 */
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DBG ("%s, ",
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((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
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DBG ("%s\n",
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((in32 (GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
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/*
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* Check if fpga's DONE signal - correctly booted ?
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*/
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/* Wait for FPGA end of programming period . */
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count = 0;
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while (!(in32 (GPIO0_IR) & FPGA_DONE)) {
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udelay (1000); /* wait 1ms */
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/* Check for timeout */
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if (count++ > 3) {
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DBG ("FPGA: Booting failed!\n");
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return ERROR_FPGA_PRG_DONE;
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}
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}
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DBG ("FPGA: Booting successful!\n");
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return 0;
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}
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#endif /* 0 */
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