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d2166319df
Add a driver to configure the SerDes (Serializer/Deserializer) lanes on the MPC83xx architecture. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
185 lines
4.5 KiB
C
185 lines
4.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2018
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* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
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*
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* base on the MPC83xx serdes initialization, which is
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*
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* Copyright 2007,2011 Freescale Semiconductor, Inc.
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* Copyright (C) 2008 MontaVista Software, Inc.
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*/
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#include <common.h>
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#include <dm.h>
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#include <mapmem.h>
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#include <misc.h>
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#include "mpc83xx_serdes.h"
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/**
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* struct mpc83xx_serdes_priv - Private structure for MPC83xx serdes
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* @regs: The device's register map
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* @rfcks: Variable to keep the serdes reference clock selection set during
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* initialization in (is or'd to every value written to SRDSCR4)
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*/
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struct mpc83xx_serdes_priv {
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struct mpc83xx_serdes_regs *regs;
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u32 rfcks;
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};
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/**
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* setup_sata() - Configure the SerDes device to SATA mode
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* @dev: The device to configure
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*/
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static void setup_sata(struct udevice *dev)
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{
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struct mpc83xx_serdes_priv *priv = dev_get_priv(dev);
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/* Set and clear reset bits */
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setbits_be32(&priv->regs->srdsrstctl, SRDSRSTCTL_SATA_RESET);
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udelay(1000);
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clrbits_be32(&priv->regs->srdsrstctl, SRDSRSTCTL_SATA_RESET);
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/* Configure SRDSCR0 */
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clrsetbits_be32(&priv->regs->srdscr0,
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SRDSCR0_TXEQA_MASK | SRDSCR0_TXEQE_MASK,
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SRDSCR0_TXEQA_SATA | SRDSCR0_TXEQE_SATA);
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/* Configure SRDSCR1 */
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clrbits_be32(&priv->regs->srdscr1, SRDSCR1_PLLBW);
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/* Configure SRDSCR2 */
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clrsetbits_be32(&priv->regs->srdscr2,
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SRDSCR2_SEIC_MASK,
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SRDSCR2_SEIC_SATA);
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/* Configure SRDSCR3 */
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out_be32(&priv->regs->srdscr3,
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SRDSCR3_KFR_SATA | SRDSCR3_KPH_SATA |
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SRDSCR3_SDFM_SATA_PEX | SRDSCR3_SDTXL_SATA);
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/* Configure SRDSCR4 */
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out_be32(&priv->regs->srdscr4, priv->rfcks | SRDSCR4_PROT_SATA);
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}
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/**
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* setup_pex() - Configure the SerDes device to PCI Express mode
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* @dev: The device to configure
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* @type: The PCI Express type to configure for (x1 or x2)
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*/
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static void setup_pex(struct udevice *dev, enum pex_type type)
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{
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struct mpc83xx_serdes_priv *priv = dev_get_priv(dev);
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/* Configure SRDSCR1 */
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setbits_be32(&priv->regs->srdscr1, SRDSCR1_PLLBW);
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/* Configure SRDSCR2 */
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clrsetbits_be32(&priv->regs->srdscr2,
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SRDSCR2_SEIC_MASK,
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SRDSCR2_SEIC_PEX);
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/* Configure SRDSCR3 */
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out_be32(&priv->regs->srdscr3, SRDSCR3_SDFM_SATA_PEX);
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/* Configure SRDSCR4 */
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if (type == PEX_X2)
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out_be32(&priv->regs->srdscr4,
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priv->rfcks | SRDSCR4_PROT_PEX | SRDSCR4_PLANE_X2);
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else
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out_be32(&priv->regs->srdscr4,
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priv->rfcks | SRDSCR4_PROT_PEX);
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}
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/**
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* setup_sgmii() - Configure the SerDes device to SGMII mode
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* @dev: The device to configure
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*/
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static void setup_sgmii(struct udevice *dev)
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{
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struct mpc83xx_serdes_priv *priv = dev_get_priv(dev);
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/* Configure SRDSCR1 */
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clrbits_be32(&priv->regs->srdscr1, SRDSCR1_PLLBW);
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/* Configure SRDSCR2 */
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clrsetbits_be32(&priv->regs->srdscr2,
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SRDSCR2_SEIC_MASK,
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SRDSCR2_SEIC_SGMII);
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/* Configure SRDSCR3 */
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out_be32(&priv->regs->srdscr3, 0);
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/* Configure SRDSCR4 */
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out_be32(&priv->regs->srdscr4, priv->rfcks | SRDSCR4_PROT_SGMII);
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}
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static int mpc83xx_serdes_probe(struct udevice *dev)
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{
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struct mpc83xx_serdes_priv *priv = dev_get_priv(dev);
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bool vdd;
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const char *proto;
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priv->regs = map_sysmem(dev_read_addr(dev),
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sizeof(struct mpc83xx_serdes_regs));
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switch (dev_read_u32_default(dev, "serdes-clk", -1)) {
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case 100:
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priv->rfcks = SRDSCR4_RFCKS_100;
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break;
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case 125:
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priv->rfcks = SRDSCR4_RFCKS_125;
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break;
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case 150:
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priv->rfcks = SRDSCR4_RFCKS_150;
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break;
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default:
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debug("%s: Could not read serdes clock value\n", dev->name);
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return -EINVAL;
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}
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vdd = dev_read_bool(dev, "vdd");
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/* 1.0V corevdd */
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if (vdd) {
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/* DPPE/DPPA = 0 */
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clrbits_be32(&priv->regs->srdscr0, SRDSCR0_DPP_1V2);
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/* VDD = 0 */
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clrbits_be32(&priv->regs->srdscr0, SRDSCR2_VDD_1V2);
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}
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proto = dev_read_string(dev, "proto");
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/* protocol specific configuration */
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if (!strcmp(proto, "sata")) {
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setup_sata(dev);
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} else if (!strcmp(proto, "pex")) {
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setup_pex(dev, PEX_X1);
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} else if (!strcmp(proto, "pex-x2")) {
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setup_pex(dev, PEX_X2);
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} else if (!strcmp(proto, "sgmii")) {
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setup_sgmii(dev);
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} else {
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debug("%s: Invalid protocol value %s\n", dev->name, proto);
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return -EINVAL;
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}
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/* Do a software reset */
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setbits_be32(&priv->regs->srdsrstctl, SRDSRSTCTL_RST);
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return 0;
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}
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static const struct udevice_id mpc83xx_serdes_ids[] = {
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{ .compatible = "fsl,mpc83xx-serdes" },
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{ }
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};
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U_BOOT_DRIVER(mpc83xx_serdes) = {
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.name = "mpc83xx_serdes",
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.id = UCLASS_MISC,
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.of_match = mpc83xx_serdes_ids,
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.probe = mpc83xx_serdes_probe,
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.priv_auto_alloc_size = sizeof(struct mpc83xx_serdes_priv),
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};
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