mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
143 lines
3 KiB
C
143 lines
3 KiB
C
/*
|
|
* Voipac PXA270 Support
|
|
*
|
|
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of
|
|
* the License, or (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
* MA 02111-1307 USA
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/arch/hardware.h>
|
|
#include <asm/arch/regs-mmc.h>
|
|
#include <asm/arch/pxa.h>
|
|
#include <netdev.h>
|
|
#include <serial.h>
|
|
#include <asm/io.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
/*
|
|
* Miscelaneous platform dependent initialisations
|
|
*/
|
|
int board_init(void)
|
|
{
|
|
/* We have RAM, disable cache */
|
|
dcache_disable();
|
|
icache_disable();
|
|
|
|
/* memory and cpu-speed are setup before relocation */
|
|
/* so we do _nothing_ here */
|
|
|
|
/* Arch number of vpac270 */
|
|
gd->bd->bi_arch_number = MACH_TYPE_VPAC270;
|
|
|
|
/* adress of boot parameters */
|
|
gd->bd->bi_boot_params = 0xa0000100;
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct serial_device *default_serial_console(void)
|
|
{
|
|
return &serial_ffuart_device;
|
|
}
|
|
|
|
int dram_init(void)
|
|
{
|
|
#ifndef CONFIG_ONENAND
|
|
pxa2xx_dram_init();
|
|
#endif
|
|
gd->ram_size = PHYS_SDRAM_1_SIZE;
|
|
return 0;
|
|
}
|
|
|
|
void dram_init_banksize(void)
|
|
{
|
|
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
|
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
|
|
|
#ifdef CONFIG_RAM_256M
|
|
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
|
|
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
|
|
#endif
|
|
}
|
|
|
|
#ifdef CONFIG_CMD_MMC
|
|
int board_mmc_init(bd_t *bis)
|
|
{
|
|
pxa_mmc_register(0);
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_CMD_USB
|
|
int usb_board_init(void)
|
|
{
|
|
writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
|
|
~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
|
|
UHCHR);
|
|
|
|
writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
|
|
|
|
while (readl(UHCHR) & UHCHR_FSBIR)
|
|
;
|
|
|
|
writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
|
|
writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
|
|
|
|
/* Clear any OTG Pin Hold */
|
|
if (readl(PSSR) & PSSR_OTGPH)
|
|
writel(readl(PSSR) | PSSR_OTGPH, PSSR);
|
|
|
|
writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
|
|
writel(readl(UHCRHDA) | 0x100, UHCRHDA);
|
|
|
|
/* Set port power control mask bits, only 3 ports. */
|
|
writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
|
|
|
|
/* enable port 2 */
|
|
writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
|
|
UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void usb_board_init_fail(void)
|
|
{
|
|
return;
|
|
}
|
|
|
|
void usb_board_stop(void)
|
|
{
|
|
writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
|
|
udelay(11);
|
|
writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
|
|
|
|
writel(readl(UHCCOMS) | 1, UHCCOMS);
|
|
udelay(10);
|
|
|
|
writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
|
|
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_DRIVER_DM9000
|
|
int board_eth_init(bd_t *bis)
|
|
{
|
|
return dm9000_initialize(bis);
|
|
}
|
|
#endif
|