mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 07:34:31 +00:00
09f3ca3dd5
We have finished Generic Board conversion for ARM and PowerPC, i.e. all the boards have been converted except OpenRISC, SuperH, SPARC, which have not supported Generic Board framework yet. Select SYS_GENERIC_BOARD in arch/Kconfig and delete all the macro defines in include/configs/*.h. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
570 lines
17 KiB
C
570 lines
17 KiB
C
/*
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* (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
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* (C) Copyright 2010 DAVE Srl <www.dave.eu>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* ifm AC14xx (MPC5121e based) board configuration file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AC14XX 1
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#define CONFIG_DISPLAY_BOARDINFO
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/*
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* Memory map for the ifm AC14xx board:
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*
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* 0x0000_0000-0x0FFF_FFFF DDR RAM (256 MB)
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* 0x3000_0000-0x3001_FFFF On Chip SRAM (128 KB)
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* 0x8000_0000-0x803F_FFFF IMMR (4 MB)
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* 0xE000_0000-0xEFFF_FFFF several LPB attached hardware (CSx)
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* 0xFC00_0000-0xFFFF_FFFF NOR Boot FLASH (64 MB)
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*/
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 Family */
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#define CONFIG_SYS_TEXT_BASE 0xFFF00000
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#if defined(CONFIG_VIDEO)
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#endif
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#define CONFIG_SYS_MPC512X_CLKIN 25000000 /* in Hz */
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#define SCFR1_IPS_DIV 2
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#define SCFR1_LPC_DIV 2
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#define SCFR1_NFC_DIV 2
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#define SCFR1_DIU_DIV 240
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#define CONFIG_MISC_INIT_R
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#define CONFIG_SYS_IMMR 0x80000000
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#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR + 0x2100)
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/* more aggressive 'mtest' over a wider address range */
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#define CONFIG_SYS_ALT_MEMTEST
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#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest region */
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#define CONFIG_SYS_MEMTEST_END 0x0FE00000
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/*
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* DDR Setup - manually set all parameters as there's no SPD etc.
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*/
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#define CONFIG_SYS_DDR_SIZE 256 /* MB */
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#define CONFIG_SYS_DDR_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
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/*
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* DDR Controller Configuration
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*
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* SYS_CFG:
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* [31:31] MDDRC Soft Reset: Diabled
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* [30:30] DRAM CKE pin: Enabled
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* [29:29] DRAM CLK: Enabled
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* [28:28] Command Mode: Enabled (For initialization only)
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* [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
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* [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
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* [20:19] Read Test: DON'T USE
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* [18:18] Self Refresh: Enabled
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* [17:17] 16bit Mode: Disabled
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* [16:13] Ready Delay: 2
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* [12:12] Half DQS Delay: Disabled
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* [11:11] Quarter DQS Delay: Disabled
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* [10:08] Write Delay: 2
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* [07:07] Early ODT: Disabled
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* [06:06] On DIE Termination: Disabled
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* [05:05] FIFO Overflow Clear: DON'T USE here
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* [04:04] FIFO Underflow Clear: DON'T USE here
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* [03:03] FIFO Overflow Pending: DON'T USE here
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* [02:02] FIFO Underlfow Pending: DON'T USE here
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* [01:01] FIFO Overlfow Enabled: Enabled
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* [00:00] FIFO Underflow Enabled: Enabled
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* TIME_CFG0
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* [31:16] DRAM Refresh Time: 0 CSB clocks
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* [15:8] DRAM Command Time: 0 CSB clocks
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* [07:00] DRAM Precharge Time: 0 CSB clocks
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* TIME_CFG1
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* [31:26] DRAM tRFC:
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* [25:21] DRAM tWR1:
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* [20:17] DRAM tWRT1:
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* [16:11] DRAM tDRR:
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* [10:05] DRAM tRC:
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* [04:00] DRAM tRAS:
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* TIME_CFG2
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* [31:28] DRAM tRCD:
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* [27:23] DRAM tFAW:
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* [22:19] DRAM tRTW1:
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* [18:15] DRAM tCCD:
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* [14:10] DRAM tRTP:
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* [09:05] DRAM tRP:
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* [04:00] DRAM tRPA
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*/
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/*
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* NOTE: although this board uses DDR1 only, the common source brings defaults
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* for DDR2 init sequences, that's why we have to keep those here as well
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*/
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/* DDR1 -- 32bit, drive strength (pad configuration) 3 for control and data */
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#define CONFIG_SYS_IOCTRL_MUX_DDR ((0 << 6) | (3 << 3) | (3 << 0))
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#define CONFIG_SYS_MDDRC_SYS_CFG (/* 0xEAA09100 */ 0 \
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| (1 << 31) /* RST_B */ \
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| (1 << 30) /* CKE */ \
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| (1 << 29) /* CLK_ON */ \
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| (0 << 28) /* CMD_MODE */ \
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| (5 << 25) /* DRAM_ROW_SELECT */ \
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| (5 << 21) /* DRAM_BANK_SELECT */ \
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| (0 << 18) /* SELF_REF_EN */ \
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| (0 << 17) /* 16BIT_MODE */ \
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| (4 << 13) /* RDLY */ \
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| (1 << 12) /* HALF_DQS_DLY */ \
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| (0 << 11) /* QUART_DQS_DLY */ \
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| (1 << 8) /* WDLY */ \
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| (0 << 7) /* EARLY_ODT */ \
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| (0 << 6) /* ON_DIE_TERMINATE */ \
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| (0 << 5) /* FIFO_OV_CLEAR */ \
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| (0 << 4) /* FIFO_UV_CLEAR */ \
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| (0 << 1) /* FIFO_OV_EN */ \
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| (0 << 0) /* FIFO_UV_EN */ \
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)
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#define CONFIG_SYS_MDDRC_TIME_CFG0 0x04E03124
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#define CONFIG_SYS_MDDRC_TIME_CFG1 0x30CA1147
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#define CONFIG_SYS_MDDRC_TIME_CFG2 0x32B10864
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/* register address only, i.e. template without values */
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#define CONFIG_SYS_MICRON_BMODE 0x01000000
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#define CONFIG_SYS_MICRON_EMODE 0x01010000
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#define CONFIG_SYS_MICRON_EMODE2 0x01020000
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#define CONFIG_SYS_MICRON_EMODE3 0x01030000
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/*
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* values for mode registers (without mode register address)
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*/
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/* CAS 2.5 (6), burst seq (0) and length 4 (2) */
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#define CONFIG_SYS_MICRON_BMODE_PARAM 0x00000062
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#define CONFIG_SYS_MICRON_BMODE_RSTDLL 0x00000100
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/* DLL enable, reduced drive strength */
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#define CONFIG_SYS_MICRON_EMODE_PARAM 0x00000002
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#define CONFIG_SYS_DDRCMD_NOP 0x01380000
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#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
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#define CONFIG_SYS_MICRON_EMR ((1 << 24) | /* CMD_REQ */ \
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(0 << 22) | /* DRAM_CS */ \
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(0 << 21) | /* DRAM_RAS */ \
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(0 << 20) | /* DRAM_CAS */ \
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(0 << 19) | /* DRAM_WEB */ \
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(1 << 16) | /* DRAM_BS[2:0] */ \
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(0 << 15) | /* */ \
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(0 << 12) | /* A12->out */ \
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(0 << 11) | /* A11->RDQS */ \
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(0 << 10) | /* A10->DQS# */ \
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(0 << 7) | /* OCD program */ \
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(0 << 6) | /* Rtt1 */ \
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(0 << 3) | /* posted CAS# */ \
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(0 << 2) | /* Rtt0 */ \
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(1 << 1) | /* ODS */ \
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(0 << 0) /* DLL */ \
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)
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#define CONFIG_SYS_MICRON_EMR2 0x01020000
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#define CONFIG_SYS_MICRON_EMR3 0x01030000
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#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
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#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
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#define CONFIG_SYS_MICRON_EMR_OCD ((1 << 24) | /* CMD_REQ */ \
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(0 << 22) | /* DRAM_CS */ \
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(0 << 21) | /* DRAM_RAS */ \
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(0 << 20) | /* DRAM_CAS */ \
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(0 << 19) | /* DRAM_WEB */ \
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(1 << 16) | /* DRAM_BS[2:0] */ \
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(0 << 15) | /* */ \
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(0 << 12) | /* A12->out */ \
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(0 << 11) | /* A11->RDQS */ \
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(1 << 10) | /* A10->DQS# */ \
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(7 << 7) | /* OCD program */ \
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(0 << 6) | /* Rtt1 */ \
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(0 << 3) | /* posted CAS# */ \
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(1 << 2) | /* Rtt0 */ \
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(0 << 1) | /* ODS */ \
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(0 << 0) /* DLL */ \
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)
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/*
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* Backward compatible definitions,
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* so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c
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*/
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#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2)
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#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3)
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#define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR)
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#define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD)
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/* DDR Priority Manager Configuration */
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#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
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#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
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#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
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#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
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#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
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#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
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#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
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#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
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#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
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#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
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#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
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#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
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#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
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#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
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#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
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#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
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#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
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#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
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#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
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#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
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#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
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#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
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#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
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/*
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* NOR FLASH on the Local Bus
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*/
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#define CONFIG_SYS_FLASH_CFI /* use the CFI code */
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#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
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#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */
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#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_FLASH_BANKS_LIST { \
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CONFIG_SYS_FLASH_BASE + 0 * CONFIG_SYS_FLASH_SIZE, \
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}
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
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#undef CONFIG_SYS_FLASH_CHECKSUM
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#define CONFIG_SYS_FLASH_PROTECTION
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/*
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* SRAM support
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*/
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#define CONFIG_SYS_SRAM_BASE 0x30000000
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#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
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/*
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* CS related parameters
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*/
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/* CS0 Flash */
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#define CONFIG_SYS_CS0_CFG 0x00031110
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#define CONFIG_SYS_CS0_START 0xFC000000
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#define CONFIG_SYS_CS0_SIZE 0x04000000
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/* CS1 FRAM */
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#define CONFIG_SYS_CS1_CFG 0x00011000
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#define CONFIG_SYS_CS1_START 0xE0000000
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#define CONFIG_SYS_CS1_SIZE 0x00010000
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/* CS2 AS-i 1 */
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#define CONFIG_SYS_CS2_CFG 0x00009100
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#define CONFIG_SYS_CS2_START 0xE0100000
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#define CONFIG_SYS_CS2_SIZE 0x00080000
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/* CS3 netX */
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#define CONFIG_SYS_CS3_CFG 0x000A1140
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#define CONFIG_SYS_CS3_START 0xE0300000
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#define CONFIG_SYS_CS3_SIZE 0x00020000
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/* CS5 safety */
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#define CONFIG_SYS_CS5_CFG 0x0011F000
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#define CONFIG_SYS_CS5_START 0xE0400000
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#define CONFIG_SYS_CS5_SIZE 0x00010000
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/* CS6 AS-i 2 */
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#define CONFIG_SYS_CS6_CFG 0x00009100
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#define CONFIG_SYS_CS6_START 0xE0200000
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#define CONFIG_SYS_CS6_SIZE 0x00080000
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/* Don't use alternative CS timing for any CS */
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#define CONFIG_SYS_CS_ALETIMING 0x00000000
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#define CONFIG_SYS_CS_BURST 0x00000000
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#define CONFIG_SYS_CS_DEADCYCLE 0x00000020
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#define CONFIG_SYS_CS_HOLDCYCLE 0x00000020
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/* Use SRAM for initial stack */
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE
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#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
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#ifdef CONFIG_FSL_DIU_FB
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#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
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#else
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
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#endif
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1
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/*
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* Serial console configuration
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*/
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#define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */
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#define CONFIG_SYS_PSC3
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#if CONFIG_PSC_CONSOLE != 3
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#error CONFIG_PSC_CONSOLE must be 3
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#endif
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#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
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#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
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#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
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#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
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#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
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/*
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* Clocks in use
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*/
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#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
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CLOCK_SCCR1_LPC_EN | \
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CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
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CLOCK_SCCR1_PSC_EN(7) | \
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CLOCK_SCCR1_PSCFIFO_EN | \
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CLOCK_SCCR1_DDR_EN | \
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CLOCK_SCCR1_FEC_EN | \
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CLOCK_SCCR1_TPR_EN)
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#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
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CLOCK_SCCR2_SPDIF_EN | \
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CLOCK_SCCR2_DIU_EN | \
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CLOCK_SCCR2_I2C_EN)
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#define CONFIG_CMDLINE_EDITING 1 /* command line history */
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/* I2C */
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#define CONFIG_HARD_I2C /* I2C with hardware support */
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#define CONFIG_I2C_MULTI_BUS
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/* I2C speed and slave address */
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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/*
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* IIM - IC Identification Module
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*/
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#undef CONFIG_FSL_IIM
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/*
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* EEPROM configuration for Atmel AT24C01:
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* 8-bit addresses, 30ms write delay, 32-Byte Page Write Mode
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*/
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 30
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
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/*
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* Ethernet configuration
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*/
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#define CONFIG_MPC512x_FEC 1
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#define CONFIG_PHY_ADDR 0x1F
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_FEC_AN_TIMEOUT 1
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#define CONFIG_HAS_ETH0
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/*
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* Environment
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1
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/* This has to be a multiple of the flash sector size */
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#define CONFIG_ENV_ADDR 0xFFF40000
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_SECT_SIZE 0x20000
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
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CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#define CONFIG_LOADS_ECHO 1
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_EEPROM
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#undef CONFIG_CMD_FUSE
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#define CONFIG_CMD_I2C
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#undef CONFIG_CMD_IDE
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#undef CONFIG_CMD_EXT2
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#if defined(CONFIG_PCI)
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#define CONFIG_CMD_PCI
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#endif
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#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
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#define CONFIG_DOS_PARTITION
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#define CONFIG_MAC_PARTITION
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#define CONFIG_ISO_PARTITION
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#endif /* defined(CONFIG_CMD_IDE) */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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#ifdef CONFIG_CMD_KGDB
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# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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/* max number of command args */
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#define CONFIG_SYS_MAXARGS 32
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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|
* the maximum mapped by the Linux kernel during initialization.
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|
*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
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|
|
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/* Cache Configuration */
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#define CONFIG_SYS_DCACHE_SIZE 32768
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#ifdef CONFIG_CMD_KGDB
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|
#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of 32 */
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#endif
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|
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#define CONFIG_SYS_HID0_INIT 0x000000000
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#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
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|
HID0_ICE)
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#define CONFIG_SYS_HID2 HID2_HBE
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|
|
|
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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|
|
|
/*
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|
* Internal Definitions
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|
*
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|
* Boot Flags
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|
*/
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|
#define BOOTFLAG_COLD 0x01
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|
#define BOOTFLAG_WARM 0x02
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|
|
|
#ifdef CONFIG_CMD_KGDB
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|
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
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|
#endif
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|
|
|
/*
|
|
* Environment Configuration
|
|
*/
|
|
#define CONFIG_ENV_OVERWRITE
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|
#define CONFIG_TIMESTAMP
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|
|
|
/* default load addr for tftp and bootm */
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|
#define CONFIG_LOADADDR 400000
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|
|
|
#define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */
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|
|
|
/* the builtin environment and standard greeting */
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|
#define CONFIG_PREBOOT "echo;" \
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|
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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|
"echo"
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|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS_DEVEL \
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|
"muster_nr=-00\0" \
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|
"fromram=run ramargs addip addtty; " \
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|
"tftp ${fdt_addr_r} ac14xx/ac14xx.dtb${muster_nr}; " \
|
|
"tftp ${kernel_addr_r} ac14xx/uImage${muster_nr}; " \
|
|
"tftp ${ramdisk_addr_r} ac14xx/uFS${muster_nr}; " \
|
|
"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
|
|
"fromnfs=run nfsargs addip addtty; " \
|
|
"tftp ${fdt_addr_r} ac14xx/ac14xx.dtb${muster_nr}; " \
|
|
"tftp ${kernel_addr_r} ac14xx/uImage${muster_nr}; " \
|
|
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
|
|
"fromflash=run nfsargs addip addtty; " \
|
|
"bootm fc020000 - fc000000\0" \
|
|
"mtdargsrec=setenv bootargs root=/dev/mtdblock1 ro\0" \
|
|
"recovery=run mtdargsrec addip addtty; " \
|
|
"bootm ffd20000 - ffee0000\0" \
|
|
"production=run ramargs addip addtty; " \
|
|
"bootm fc020000 fc400000 fc000000\0" \
|
|
"mtdargs=setenv bootargs root=/dev/mtdblock1 ro\0" \
|
|
"prodmtd=run mtdargs addip addtty; " \
|
|
"bootm fc020000 - fc000000\0" \
|
|
""
|
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
"u-boot_addr_r=200000\0" \
|
|
"kernel_addr_r=600000\0" \
|
|
"fdt_addr_r=a00000\0" \
|
|
"ramdisk_addr_r=b00000\0" \
|
|
"u-boot_addr=FFF00000\0" \
|
|
"kernel_addr=FC020000\0" \
|
|
"fdt_addr=FC000000\0" \
|
|
"ramdisk_addr=FC400000\0" \
|
|
"verify=n\0" \
|
|
"ramdiskfile=ac14xx/uRamdisk\0" \
|
|
"u-boot=ac14xx/u-boot.bin\0" \
|
|
"bootfile=ac14xx/uImage\0" \
|
|
"fdtfile=ac14xx/ac14xx.dtb\0" \
|
|
"netdev=eth0\0" \
|
|
"consdev=ttyPSC0\0" \
|
|
"hostname=ac14xx\0" \
|
|
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
|
"nfsroot=${serverip}:${rootpath}${muster_nr}\0" \
|
|
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
|
"addip=setenv bootargs ${bootargs} " \
|
|
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
|
":${hostname}:${netdev}:off panic=1\0" \
|
|
"addtty=setenv bootargs ${bootargs} " \
|
|
"console=${consdev},${baudrate}\0" \
|
|
"flash_nfs=run nfsargs addip addtty;" \
|
|
"bootm ${kernel_addr} - ${fdt_addr}\0" \
|
|
"flash_self=run ramargs addip addtty;" \
|
|
"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
|
|
"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
|
|
"tftp ${fdt_addr_r} ${fdtfile};" \
|
|
"run nfsargs addip addtty;" \
|
|
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
|
|
"net_self=tftp ${kernel_addr_r} ${bootfile};" \
|
|
"tftp ${ramdisk_addr_r} ${ramdiskfile};" \
|
|
"tftp ${fdt_addr_r} ${fdtfile};" \
|
|
"run ramargs addip addtty;" \
|
|
"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
|
|
"load=tftp ${u-boot_addr_r} ${u-boot}\0" \
|
|
"update=protect off ${u-boot_addr} +${filesize};" \
|
|
"era ${u-boot_addr} +${filesize};" \
|
|
"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
|
|
CONFIG_EXTRA_ENV_SETTINGS_DEVEL \
|
|
"upd=run load update\0" \
|
|
""
|
|
|
|
#define CONFIG_BOOTCOMMAND "run production"
|
|
|
|
#define CONFIG_ARP_TIMEOUT 200UL
|
|
|
|
#define CONFIG_FIT 1
|
|
#define CONFIG_OF_LIBFDT 1
|
|
#define CONFIG_OF_BOARD_SETUP 1
|
|
#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
|
|
|
|
#define OF_CPU "PowerPC,5121@0"
|
|
#define OF_SOC_COMPAT "fsl,mpc5121-immr"
|
|
#define OF_TBCLK (bd->bi_busfreq / 4)
|
|
#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
|
|
|
|
#endif /* __CONFIG_H */
|