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a836626cc4
The work-around for P4080 erratum SERDES9 says that the SERDES receiver lanes should be reset after the XAUI starts tranmitting alignment signals. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
114 lines
3 KiB
C
114 lines
3 KiB
C
/*
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* Teranetics PHY drivers
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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* author Andy Fleming
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*
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*/
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#include <config.h>
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#include <common.h>
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#include <phy.h>
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#ifndef CONFIG_PHYLIB_10G
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#error The Teranetics PHY needs 10G support
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#endif
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int tn2020_config(struct phy_device *phydev)
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{
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if (phydev->port == PORT_FIBRE) {
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unsigned short restart_an = (MDIO_AN_CTRL1_RESTART |
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MDIO_AN_CTRL1_ENABLE |
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MDIO_AN_CTRL1_XNP);
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phy_write(phydev, 30, 93, 2);
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phy_write(phydev, MDIO_MMD_AN, MDIO_CTRL1, restart_an);
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}
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return 0;
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}
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int tn2020_startup(struct phy_device *phydev)
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{
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unsigned int timeout = 5 * 1000; /* 5 second timeout */
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#define MDIO_PHYXS_LANE_READY (MDIO_PHYXS_LNSTAT_SYNC0 | \
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MDIO_PHYXS_LNSTAT_SYNC1 | \
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MDIO_PHYXS_LNSTAT_SYNC2 | \
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MDIO_PHYXS_LNSTAT_SYNC3 | \
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MDIO_PHYXS_LNSTAT_ALIGN)
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/*
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* Wait for the XAUI-SERDES lanes to align first. Under normal
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* circumstances, this can take up to three seconds.
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*/
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while (--timeout) {
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int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_LNSTAT);
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if (reg < 0) {
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printf("TN2020: Error reading from PHY at "
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"address %u\n", phydev->addr);
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break;
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}
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if ((reg & MDIO_PHYXS_LANE_READY) == MDIO_PHYXS_LANE_READY)
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break;
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udelay(1000);
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}
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if (!timeout) {
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/*
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* A timeout is bad, but it may not be fatal, so don't
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* return an error. Display a warning instead.
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*/
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printf("TN2020: Timeout waiting for PHY at address %u to "
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"align.\n", phydev->addr);
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}
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if (phydev->port != PORT_FIBRE)
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return gen10g_startup(phydev);
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/*
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* The TN2020 only pretends to support fiber.
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* It works, but it doesn't look like it works,
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* so the link status reports no link.
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*/
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phydev->link = 1;
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/* For now just lie and say it's 10G all the time */
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phydev->speed = SPEED_10000;
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phydev->duplex = DUPLEX_FULL;
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return 0;
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}
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struct phy_driver tn2020_driver = {
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.name = "Teranetics TN2020",
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.uid = PHY_UID_TN2020,
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.mask = 0xfffffff0,
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.features = PHY_10G_FEATURES,
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.mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
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MDIO_DEVS_PHYXS | MDIO_DEVS_AN |
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MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2),
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.config = &tn2020_config,
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.startup = &tn2020_startup,
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.shutdown = &gen10g_shutdown,
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};
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int phy_teranetics_init(void)
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{
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phy_register(&tn2020_driver);
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return 0;
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}
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