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EMIF tool for AM64 SK is now updated to 0.8.0 that includes * disabled Write DQ training * improve CA ODT to 60 ohms The lpddr4 enabled with periodic WDQ training is causing periodic 26us stall. This makes the SoC stall without doing anything which leads to R5 interrupt latency in TCM memory. Due to this periodic training there are some outstanding CPU transactions waiting for the lpddr4 to complete. Hence, disable the periodic write DQ training during the non-initialization stage of lpddr4 which results in an approximate 1us stall. Also, update the lpddr4 config to improve CA ODT by 60 ohms The rationales are as follows: - PI_WDQLVL_EN: 2 Bits register field to support write DQ leveling, disable bit 1 that supports Write DQ during non-initialization to avoid ~26us stall during code execution. - MR11_DATA_F1/F2_x register fields value changed to 0x66 that changes the CA ODT from 48ohm to 60ohm to improve the eye margin on CA bus by increasing the signal swing. Signed-off-by: James Doublesin <doublesin@ti.com> Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> |
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