mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-02 01:19:49 +00:00
38d4a6042b
Fix build failure due the move of mx28 code to 'mxs' SoC. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
113 lines
2.6 KiB
C
113 lines
2.6 KiB
C
/*
|
|
* SchulerControl GmbH, SC_SPS_1 module
|
|
*
|
|
* Copyright (C) 2012 Marek Vasut <marex@denx.de>
|
|
* on behalf of DENX Software Engineering GmbH
|
|
*
|
|
* See file CREDITS for list of people who contributed to this
|
|
* project.
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of
|
|
* the License, or (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
* MA 02111-1307 USA
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/gpio.h>
|
|
#include <asm/io.h>
|
|
#include <asm/arch/imx-regs.h>
|
|
#include <asm/arch/iomux-mx28.h>
|
|
#include <asm/arch/clock.h>
|
|
#include <asm/arch/sys_proto.h>
|
|
#include <linux/mii.h>
|
|
#include <miiphy.h>
|
|
#include <netdev.h>
|
|
#include <errno.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
/*
|
|
* Functions
|
|
*/
|
|
int board_early_init_f(void)
|
|
{
|
|
/* IO0 clock at 480MHz */
|
|
mx28_set_ioclk(MXC_IOCLK0, 480000);
|
|
/* IO1 clock at 480MHz */
|
|
mx28_set_ioclk(MXC_IOCLK1, 480000);
|
|
|
|
/* SSP0 clock at 96MHz */
|
|
mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
|
|
/* SSP2 clock at 96MHz */
|
|
mx28_set_sspclk(MXC_SSPCLK2, 96000, 0);
|
|
|
|
#ifdef CONFIG_CMD_USB
|
|
mxs_iomux_setup_pad(MX28_PAD_AUART1_CTS__USB0_OVERCURRENT);
|
|
mxs_iomux_setup_pad(MX28_PAD_AUART2_TX__GPIO_3_9 |
|
|
MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL);
|
|
gpio_direction_output(MX28_PAD_AUART2_TX__GPIO_3_9, 1);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_init(void)
|
|
{
|
|
/* Adress of boot parameters */
|
|
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int dram_init(void)
|
|
{
|
|
return mx28_dram_init();
|
|
}
|
|
|
|
#ifdef CONFIG_CMD_MMC
|
|
int board_mmc_init(bd_t *bis)
|
|
{
|
|
return mxsmmc_initialize(bis, 0, NULL);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_CMD_NET
|
|
int board_eth_init(bd_t *bis)
|
|
{
|
|
struct mxs_clkctrl_regs *clkctrl_regs =
|
|
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
|
|
int ret;
|
|
|
|
ret = cpu_eth_init(bis);
|
|
|
|
clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
|
|
CLKCTRL_ENET_TIME_SEL_MASK,
|
|
CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN);
|
|
|
|
ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
|
|
if (ret) {
|
|
printf("FEC MXS: Unable to init FEC0\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE);
|
|
if (ret) {
|
|
printf("FEC MXS: Unable to init FEC1\n");
|
|
return ret;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
#endif
|