mirror of
https://github.com/AsahiLinux/u-boot
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5da627a424
- Add support for Altera FPGA ACEX1K
* Patches by Thomas Lange, 09 Oct 2003:
- Endian swap ATA identity for all big endian CPUs, not just PPC
- MIPS only: New option CONFIG_MEMSIZE_IN_BYTES for passing memsize
args to linux
- add support for dbau1x00 board (MIPS32)
123 lines
2.9 KiB
C
123 lines
2.9 KiB
C
/*
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* AU1X00 UART support
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*
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* Hardcoded to UART 0 for now
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* Speed and options also hardcoded to 115200 8N1
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*
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* Copyright (c) 2003 Thomas.Lange@corelatus.se
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#ifdef CONFIG_AU1X00
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#include <common.h>
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#include <asm/au1x00.h>
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/******************************************************************************
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*
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* serial_init - initialize a channel
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*
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* This routine initializes the number of data bits, parity
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* and set the selected baud rate. Interrupts are disabled.
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* Set the modem control signals if the option is selected.
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*
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* RETURNS: N/A
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*/
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int serial_init (void)
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{
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volatile u32 *uart_fifoctl = (volatile u32*)(UART0_ADDR+UART_FCR);
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volatile u32 *uart_enable = (volatile u32*)(UART0_ADDR+UART_ENABLE);
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/* Enable clocks first */
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*uart_enable = UART_EN_CE;
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/* Then release reset */
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/* Must release reset before setting other regs */
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*uart_enable = UART_EN_CE|UART_EN_E;
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/* Activate fifos, reset tx and rx */
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/* Set tx trigger level to 12 */
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*uart_fifoctl = UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|
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UART_FCR_CLEAR_XMIT|UART_FCR_T_TRIGGER_12;
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serial_setbrg();
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return 0;
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}
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void serial_setbrg (void)
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{
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volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK);
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volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR);
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/* Set baudrate to 115200 */
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*uart_clk = 0x36;
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/* Set parity, stop bits and word length to 8N1 */
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*uart_lcr = UART_LCR_WLEN8;
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}
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void serial_putc (const char c)
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{
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volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
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volatile u32 *uart_tx = (volatile u32*)(UART0_ADDR+UART_TX);
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if (c == '\n') serial_putc ('\r');
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/* Wait for fifo to shift out some bytes */
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while((*uart_lsr&UART_LSR_THRE)==0);
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*uart_tx = (u32)c;
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}
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void serial_puts (const char *s)
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{
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while (*s)
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{
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serial_putc (*s++);
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}
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}
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int serial_getc (void)
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{
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volatile u32 *uart_rx = (volatile u32*)(UART0_ADDR+UART_RX);
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char c;
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while (!serial_tstc());
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c = (*uart_rx&0xFF);
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return c;
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}
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int serial_tstc (void)
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{
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volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
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if(*uart_lsr&UART_LSR_DR){
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/* Data in rfifo */
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return(1);
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}
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return 0;
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}
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#endif /* CONFIG_SERIAL_AU1X00 */
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