mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-27 07:01:24 +00:00
8bde7f776c
- remove trailing white space, trailing empty lines, C++ comments, etc.
- split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
* Patches by Kenneth Johansson, 25 Jun 2003:
- major rework of command structure
(work done mostly by Michal Cendrowski and Joakim Kristiansen)
501 lines
11 KiB
C
501 lines
11 KiB
C
/*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* stuff specific for the sc520,
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* but idependent of implementation */
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#include <config.h>
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#ifdef CONFIG_SC520
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#include <common.h>
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#include <config.h>
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#include <pci.h>
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#include <ssi.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <asm/ic/sc520.h>
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/*
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* utility functions for boards based on the AMD sc520
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*
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* void write_mmcr_byte(u16 mmcr, u8 data)
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* void write_mmcr_word(u16 mmcr, u16 data)
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* void write_mmcr_long(u16 mmcr, u32 data)
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*
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* u8 read_mmcr_byte(u16 mmcr)
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* u16 read_mmcr_word(u16 mmcr)
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* u32 read_mmcr_long(u16 mmcr)
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*
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* void init_sc520(void)
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* unsigned long init_sc520_dram(void)
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* void pci_sc520_init(struct pci_controller *hose)
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*
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* void reset_timer(void)
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* ulong get_timer(ulong base)
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* void set_timer(ulong t)
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* void udelay(unsigned long usec)
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*
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*/
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static u32 mmcr_base= 0xfffef000;
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void write_mmcr_byte(u16 mmcr, u8 data)
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{
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writeb(data, mmcr+mmcr_base);
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}
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void write_mmcr_word(u16 mmcr, u16 data)
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{
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writew(data, mmcr+mmcr_base);
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}
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void write_mmcr_long(u16 mmcr, u32 data)
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{
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writel(data, mmcr+mmcr_base);
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}
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u8 read_mmcr_byte(u16 mmcr)
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{
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return readb(mmcr+mmcr_base);
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}
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u16 read_mmcr_word(u16 mmcr)
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{
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return readw(mmcr+mmcr_base);
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}
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u32 read_mmcr_long(u16 mmcr)
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{
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return readl(mmcr+mmcr_base);
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}
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void init_sc520(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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/* Set the UARTxCTL register at it's slower,
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* baud clock giving us a 1.8432 MHz reference
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*/
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write_mmcr_byte(SC520_UART1CTL, 7);
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write_mmcr_byte(SC520_UART2CTL, 7);
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/* first set the timer pin mapping */
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write_mmcr_byte(SC520_CLKSEL, 0x72); /* no clock frequency selected, use 1.1892MHz */
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/* enable PCI bus arbitrer */
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write_mmcr_byte(SC520_SYSARBCTL,0x02); /* enable concurrent mode */
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write_mmcr_word(SC520_SYSARBMENB,0x1f); /* enable external grants */
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write_mmcr_word(SC520_HBCTL,0x04); /* enable posted-writes */
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if (CFG_SC520_HIGH_SPEED) {
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write_mmcr_byte(SC520_CPUCTL, 0x2); /* set it to 133 MHz and write back */
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gd->cpu_clk = 133000000;
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printf("## CPU Speed set to 133MHz\n");
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} else {
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write_mmcr_byte(SC520_CPUCTL, 1); /* set CPU to 100 MHz and write back cache */
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printf("## CPU Speed set to 100MHz\n");
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gd->cpu_clk = 100000000;
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}
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/* wait at least one millisecond */
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asm("movl $0x2000,%%ecx\n"
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"wait_loop: pushl %%ecx\n"
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"popl %%ecx\n"
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"loop wait_loop\n": : : "ecx");
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/* turn on the SDRAM write buffer */
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write_mmcr_byte(SC520_DBCTL, 0x11);
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/* turn on the cache and disable write through */
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asm("movl %%cr0, %%eax\n"
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"andl $0x9fffffff, %%eax\n"
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"movl %%eax, %%cr0\n" : : : "eax");
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}
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unsigned long init_sc520_dram(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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bd_t *bd = gd->bd;
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u32 dram_present=0;
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u32 dram_ctrl;
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int val;
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int cas_precharge_delay = CFG_SDRAM_PRECHARGE_DELAY;
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int refresh_rate = CFG_SDRAM_REFRESH_RATE;
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int ras_cas_delay = CFG_SDRAM_RAS_CAS_DELAY;
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/* set SDRAM speed here */
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refresh_rate/=78;
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if (refresh_rate<=1) {
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val = 0; /* 7.8us */
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} else if (refresh_rate==2) {
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val = 1; /* 15.6us */
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} else if (refresh_rate==3 || refresh_rate==4) {
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val = 2; /* 31.2us */
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} else {
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val = 3; /* 62.4us */
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}
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write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4));
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val = read_mmcr_byte(SC520_DRCTMCTL);
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val &= 0xf0;
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if (cas_precharge_delay==3) {
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val |= 0x04; /* 3T */
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} else if (cas_precharge_delay==4) {
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val |= 0x08; /* 4T */
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} else if (cas_precharge_delay>4) {
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val |= 0x0c;
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}
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if (ras_cas_delay > 3) {
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val |= 2;
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} else {
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val |= 1;
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}
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write_mmcr_byte(SC520_DRCTMCTL, val);
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/* We read-back the configuration of the dram
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* controller that the assembly code wrote */
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dram_ctrl = read_mmcr_long(SC520_DRCBENDADR);
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bd->bi_dram[0].start = 0;
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if (dram_ctrl & 0x80) {
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/* bank 0 enabled */
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dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
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bd->bi_dram[0].size = bd->bi_dram[1].start;
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} else {
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bd->bi_dram[0].size = 0;
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bd->bi_dram[1].start = bd->bi_dram[0].start;
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}
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if (dram_ctrl & 0x8000) {
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/* bank 1 enabled */
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dram_present = bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14;
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bd->bi_dram[1].size = bd->bi_dram[2].start - bd->bi_dram[1].start;
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} else {
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bd->bi_dram[1].size = 0;
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bd->bi_dram[2].start = bd->bi_dram[1].start;
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}
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if (dram_ctrl & 0x800000) {
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/* bank 2 enabled */
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dram_present = bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6;
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bd->bi_dram[2].size = bd->bi_dram[3].start - bd->bi_dram[2].start;
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} else {
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bd->bi_dram[2].size = 0;
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bd->bi_dram[3].start = bd->bi_dram[2].start;
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}
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if (dram_ctrl & 0x80000000) {
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/* bank 3 enabled */
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dram_present = (dram_ctrl & 0x7f000000) >> 2;
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bd->bi_dram[3].size = dram_present - bd->bi_dram[3].start;
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} else {
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bd->bi_dram[3].size = 0;
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}
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#if 0
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printf("Configured %d bytes of dram\n", dram_present);
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#endif
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gd->ram_size = dram_present;
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return dram_present;
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}
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#ifdef CONFIG_PCI
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static struct {
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u8 priority;
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u16 level_reg;
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u8 level_bit;
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} sc520_irq[] = {
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{ SC520_IRQ0, SC520_MPICMODE, 0x01 },
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{ SC520_IRQ1, SC520_MPICMODE, 0x02 },
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{ SC520_IRQ2, SC520_SL1PICMODE, 0x02 },
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{ SC520_IRQ3, SC520_MPICMODE, 0x08 },
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{ SC520_IRQ4, SC520_MPICMODE, 0x10 },
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{ SC520_IRQ5, SC520_MPICMODE, 0x20 },
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{ SC520_IRQ6, SC520_MPICMODE, 0x40 },
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{ SC520_IRQ7, SC520_MPICMODE, 0x80 },
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{ SC520_IRQ8, SC520_SL1PICMODE, 0x01 },
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{ SC520_IRQ9, SC520_SL1PICMODE, 0x02 },
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{ SC520_IRQ10, SC520_SL1PICMODE, 0x04 },
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{ SC520_IRQ11, SC520_SL1PICMODE, 0x08 },
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{ SC520_IRQ12, SC520_SL1PICMODE, 0x10 },
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{ SC520_IRQ13, SC520_SL1PICMODE, 0x20 },
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{ SC520_IRQ14, SC520_SL1PICMODE, 0x40 },
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{ SC520_IRQ15, SC520_SL1PICMODE, 0x80 }
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};
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/* The interrupt used for PCI INTA-INTD */
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int sc520_pci_ints[15] = {
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1
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};
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/* utility function to configure a pci interrupt */
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int pci_sc520_set_irq(int pci_pin, int irq)
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{
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int i;
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# if 0
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printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
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#endif
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if (irq < 0 || irq > 15) {
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return -1; /* illegal irq */
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}
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if (pci_pin < 0 || pci_pin > 15) {
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return -1; /* illegal pci int pin */
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}
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/* first disable any non-pci interrupt source that use
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* this level */
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for (i=SC520_GPTMR0MAP;i<=SC520_GP10IMAP;i++) {
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if (i>=SC520_PCIINTAMAP&&i<=SC520_PCIINTDMAP) {
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continue;
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}
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if (read_mmcr_byte(i) == sc520_irq[irq].priority) {
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write_mmcr_byte(i, SC520_IRQ_DISABLED);
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}
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}
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/* Set the trigger to level */
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write_mmcr_byte(sc520_irq[irq].level_reg,
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read_mmcr_byte(sc520_irq[irq].level_reg) | sc520_irq[irq].level_bit);
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if (pci_pin < 4) {
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/* PCI INTA-INTD */
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/* route the interrupt */
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write_mmcr_byte(SC520_PCIINTAMAP + pci_pin, sc520_irq[irq].priority);
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} else {
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/* GPIRQ0-GPIRQ10 used for additional PCI INTS */
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write_mmcr_byte(SC520_GP0IMAP + pci_pin - 4, sc520_irq[irq].priority);
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/* also set the polarity in this case */
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write_mmcr_word(SC520_INTPINPOL,
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read_mmcr_word(SC520_INTPINPOL) | (1 << (pci_pin-4)));
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}
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/* register the pin */
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sc520_pci_ints[pci_pin] = irq;
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return 0; /* OK */
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}
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void pci_sc520_init(struct pci_controller *hose)
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{
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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/* System memory space */
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pci_set_region(hose->regions + 0,
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SC520_PCI_MEMORY_BUS,
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SC520_PCI_MEMORY_PHYS,
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SC520_PCI_MEMORY_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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/* PCI memory space */
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pci_set_region(hose->regions + 1,
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SC520_PCI_MEM_BUS,
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SC520_PCI_MEM_PHYS,
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SC520_PCI_MEM_SIZE,
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PCI_REGION_MEM);
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/* ISA/PCI memory space */
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pci_set_region(hose->regions + 2,
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SC520_ISA_MEM_BUS,
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SC520_ISA_MEM_PHYS,
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SC520_ISA_MEM_SIZE,
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PCI_REGION_MEM);
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/* PCI I/O space */
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pci_set_region(hose->regions + 3,
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SC520_PCI_IO_BUS,
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SC520_PCI_IO_PHYS,
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SC520_PCI_IO_SIZE,
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PCI_REGION_IO);
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/* ISA/PCI I/O space */
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pci_set_region(hose->regions + 4,
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SC520_ISA_IO_BUS,
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SC520_ISA_IO_PHYS,
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SC520_ISA_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 5;
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pci_setup_type1(hose,
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SC520_REG_ADDR,
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SC520_REG_DATA);
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pci_register_hose(hose);
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hose->last_busno = pci_hose_scan(hose);
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/* enable target memory acceses on host brige */
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pci_write_config_word(0, PCI_COMMAND,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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}
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#endif
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#ifdef CFG_TIMER_SC520
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void reset_timer(void)
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{
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write_mmcr_word(SC520_GPTMR0CNT, 0);
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write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
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}
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ulong get_timer(ulong base)
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{
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/* fixme: 30 or 33 */
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return read_mmcr_word(SC520_GPTMR0CNT) / 33;
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}
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void set_timer(ulong t)
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{
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/* FixMe: use two cascade coupled timers */
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write_mmcr_word(SC520_GPTMR0CTL, 0x4001);
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write_mmcr_word(SC520_GPTMR0CNT, t*33);
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write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
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}
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void udelay(unsigned long usec)
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{
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int m=0;
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long u;
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read_mmcr_word(SC520_SWTMRMILLI);
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read_mmcr_word(SC520_SWTMRMICRO);
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#if 0
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/* do not enable this line, udelay is used in the serial driver -> recursion */
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printf("udelay: %ld m.u %d.%d tm.tu %d.%d\n", usec, m, u, tm, tu);
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#endif
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while (1) {
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m += read_mmcr_word(SC520_SWTMRMILLI);
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u = read_mmcr_word(SC520_SWTMRMICRO) + (m * 1000);
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if (usec <= u) {
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break;
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}
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}
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}
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#endif
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int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
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{
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u8 temp=0;
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if (freq >= 8192) {
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temp |= CTL_CLK_SEL_4;
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} else if (freq >= 4096) {
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temp |= CTL_CLK_SEL_8;
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} else if (freq >= 2048) {
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temp |= CTL_CLK_SEL_16;
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} else if (freq >= 1024) {
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temp |= CTL_CLK_SEL_32;
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} else if (freq >= 512) {
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temp |= CTL_CLK_SEL_64;
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} else if (freq >= 256) {
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temp |= CTL_CLK_SEL_128;
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} else if (freq >= 128) {
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temp |= CTL_CLK_SEL_256;
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} else {
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temp |= CTL_CLK_SEL_512;
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}
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if (!lsb_first) {
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temp |= MSBF_ENB;
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}
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if (inv_clock) {
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temp |= CLK_INV_ENB;
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}
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if (inv_phase) {
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temp |= PHS_INV_ENB;
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}
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write_mmcr_byte(SC520_SSICTL, temp);
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return 0;
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}
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u8 ssi_txrx_byte(u8 data)
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{
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write_mmcr_byte(SC520_SSIXMIT, data);
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while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
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write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMITRCV);
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while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
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return read_mmcr_byte(SC520_SSIRCV);
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}
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void ssi_tx_byte(u8 data)
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{
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write_mmcr_byte(SC520_SSIXMIT, data);
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while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
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write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMIT);
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}
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u8 ssi_rx_byte(void)
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{
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while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
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write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_RCV);
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while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
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return read_mmcr_byte(SC520_SSIRCV);
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}
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#endif /* CONFIG_SC520 */
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