Pavel Machek 45d6e67710 arm: socfpga: misc: Add proper ethernet initialization ... Add function to initialize the EMAC blocks upon board startup. The preprocessor guards against building on SoCFPGA-VT and against SPL build are not needed as those are handled implicitly via both SPL framework and the socfpga_cyclone5.h config file, which will not define CONFIG_DESIGNWARE_ETH if building for SoCFPGA-VT. We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs. Once there is hardware using both EMAC blocks, this ifdef will have to go. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>		2014-10-06 17:46:49 +02:00
..
clock_manager.c	arm: socfpga: clock: Sync with reference code	2014-10-06 17:46:49 +02:00
config.mk	socfpga: Fix SOCFPGA build error for Altera dev kit	2014-08-29 15:50:54 -04:00
freeze_controller.c	socfpga: Adding Freeze Controller driver	2013-12-03 14:38:56 +01:00
lowlevel_init.S	arm: move exception handling out of start.S files	2014-05-15 16:24:53 +02:00
Makefile	socfpga: Adding Scan Manager driver	2014-07-05 00:27:27 +02:00
misc.c	arm: socfpga: misc: Add proper ethernet initialization	2014-10-06 17:46:49 +02:00
reset_manager.c	arm: socfpga: reset: Add EMAC reset functions	2014-10-06 17:46:49 +02:00
scan_manager.c	socfpga: Adding Scan Manager driver	2014-07-05 00:27:27 +02:00
spl.c	arm: socfpga: clock: Clean up bit definitions	2014-10-06 17:46:49 +02:00
system_manager.c	arm: socfpga: sysmgr: Clean up system manager	2014-10-06 17:46:48 +02:00
timer.c	arm: socfpga: timer: Pull the timer reload value from config file	2014-10-06 17:46:49 +02:00
u-boot-spl.lds	arm: Add missing .vectors section to linker scripts	2014-08-30 07:46:41 -04:00