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https://github.com/AsahiLinux/u-boot
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4833b0939a
The total RAM size of the IGEP-based boards is 512MiB not 1GiB, the LPDDR memory consist on two dies of 256MiB. Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com> Tested-by: Javier Martinez Canillas <javier@dowhile0.org>
118 lines
2.8 KiB
C
118 lines
2.8 KiB
C
/*
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* (C) Copyright 2010
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* ISEE 2007 SL, <www.iseebcn.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <twl4030.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-types.h>
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#include "igep0030.h"
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Routine: board_init
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* Description: Early hardware init.
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*/
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int board_init(void)
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{
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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/*
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* Routine: omap_rev_string
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* Description: For SPL builds output board rev
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*/
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void omap_rev_string(void)
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{
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}
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/*
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* Routine: get_board_mem_timings
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* Description: If we use SPL then there is no x-loader nor config header
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* so we have to setup the DDR timings ourself on both banks.
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*/
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void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
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u32 *mr)
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{
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*mr = MICRON_V_MR_165;
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#ifdef CONFIG_BOOT_NAND
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*mcfg = MICRON_V_MCFG_200(256 << 20);
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*ctrla = MICRON_V_ACTIMA_200;
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*ctrlb = MICRON_V_ACTIMB_200;
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*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
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#else
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if (get_cpu_family() == CPU_OMAP34XX) {
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*mcfg = NUMONYX_V_MCFG_165(256 << 20);
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*ctrla = NUMONYX_V_ACTIMA_165;
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*ctrlb = NUMONYX_V_ACTIMB_165;
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*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
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} else {
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*mcfg = NUMONYX_V_MCFG_200(256 << 20);
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*ctrla = NUMONYX_V_ACTIMA_200;
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*ctrlb = NUMONYX_V_ACTIMB_200;
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*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
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}
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#endif
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}
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#endif
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#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
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int board_mmc_init(bd_t *bis)
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{
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omap_mmc_init(0, 0, 0);
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return 0;
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}
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#endif
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/*
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* Routine: misc_init_r
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* Description: Configure board specific parts
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*/
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int misc_init_r(void)
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{
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twl4030_power_init();
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dieid_num_r();
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return 0;
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}
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/*
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers specific to the
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* hardware. Many pins need to be moved from protect to primary
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* mode.
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*/
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void set_muxconf_regs(void)
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{
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MUX_DEFAULT();
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}
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