mirror of
https://github.com/AsahiLinux/u-boot
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c05ed00afb
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
269 lines
6.1 KiB
C
269 lines
6.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2014-2019, Toradex AG
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*/
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/*
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* Helpers for Freescale PMIC PF0100
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*/
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#include <common.h>
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#include <command.h>
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#include <i2c.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <linux/delay.h>
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#include "pf0100_otp.inc"
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#include "pf0100.h"
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/* define for PMIC register dump */
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/*#define DEBUG */
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#define WARNBAR "@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\n"
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/* use GPIO: EXT_IO1 to switch on VPGM, ON: 1 */
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static __maybe_unused iomux_v3_cfg_t const pmic_prog_pads[] = {
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MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
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# define PMIC_PROG_VOLTAGE IMX_GPIO_NR(2, 3)
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};
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unsigned pmic_init(void)
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{
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int rc;
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struct udevice *dev = NULL;
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unsigned programmed = 0;
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uchar bus = 1;
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uchar devid, revid, val;
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puts("PMIC: ");
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rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev);
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if (rc) {
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printf("failed to get device for PMIC at address 0x%x\n",
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PFUZE100_I2C_ADDR);
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return 0;
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}
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/* check for errors in PMIC fuses */
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if (dm_i2c_read(dev, PFUZE100_INTSTAT3, &val, 1) < 0) {
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puts("i2c pmic INTSTAT3 register read failed\n");
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return 0;
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}
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if (val & PFUZE100_BIT_OTP_ECCI) {
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puts("\n" WARNBAR);
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puts("WARNING: ecc errors found in pmic fuse banks\n");
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puts(WARNBAR);
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}
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if (dm_i2c_read(dev, PFUZE100_OTP_ECC_SE1, &val, 1) < 0) {
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puts("i2c pmic ECC_SE1 register read failed\n");
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return 0;
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}
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if (val & PFUZE100_BITS_ECC_SE1) {
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puts(WARNBAR);
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puts("WARNING: ecc has made bit corrections in banks 1 to 5\n");
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puts(WARNBAR);
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}
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if (dm_i2c_read(dev, PFUZE100_OTP_ECC_SE2, &val, 1) < 0) {
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puts("i2c pmic ECC_SE2 register read failed\n");
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return 0;
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}
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if (val & PFUZE100_BITS_ECC_SE2) {
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puts(WARNBAR);
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puts("WARNING: ecc has made bit corrections in banks 6 to 10\n"
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);
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puts(WARNBAR);
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}
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if (dm_i2c_read(dev, PFUZE100_OTP_ECC_DE1, &val, 1) < 0) {
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puts("i2c pmic ECC_DE register read failed\n");
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return 0;
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}
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if (val & PFUZE100_BITS_ECC_DE1) {
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puts(WARNBAR);
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puts("ERROR: banks 1 to 5 have uncorrectable bits\n");
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puts(WARNBAR);
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}
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if (dm_i2c_read(dev, PFUZE100_OTP_ECC_DE2, &val, 1) < 0) {
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puts("i2c pmic ECC_DE register read failed\n");
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return 0;
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}
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if (val & PFUZE100_BITS_ECC_DE2) {
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puts(WARNBAR);
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puts("ERROR: banks 6 to 10 have uncorrectable bits\n");
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puts(WARNBAR);
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}
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/* get device ident */
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if (dm_i2c_read(dev, PFUZE100_DEVICEID, &devid, 1) < 0) {
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puts("i2c pmic devid read failed\n");
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return 0;
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}
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if (dm_i2c_read(dev, PFUZE100_REVID, &revid, 1) < 0) {
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puts("i2c pmic revid read failed\n");
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return 0;
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}
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printf("device id: 0x%.2x, revision id: 0x%.2x, ", devid, revid);
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/* get device programmed state */
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val = PFUZE100_PAGE_REGISTER_PAGE1;
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if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
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puts("i2c write failed\n");
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return 0;
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}
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if (dm_i2c_read(dev, PFUZE100_FUSE_POR1, &val, 1) < 0) {
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puts("i2c fuse_por read failed\n");
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return 0;
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}
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if (val & PFUZE100_FUSE_POR_M)
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programmed++;
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if (dm_i2c_read(dev, PFUZE100_FUSE_POR2, &val, 1) < 0) {
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puts("i2c fuse_por read failed\n");
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return programmed;
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}
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if (val & PFUZE100_FUSE_POR_M)
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programmed++;
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if (dm_i2c_read(dev, PFUZE100_FUSE_POR3, &val, 1) < 0) {
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puts("i2c fuse_por read failed\n");
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return programmed;
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}
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if (val & PFUZE100_FUSE_POR_M)
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programmed++;
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switch (programmed) {
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case 0:
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puts("not programmed\n");
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break;
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case 3:
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puts("programmed\n");
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break;
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default:
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puts("undefined programming state\n");
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break;
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}
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#ifdef DEBUG
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{
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unsigned int i, j;
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for (i = 0; i < 16; i++)
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printf("\t%x", i);
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for (j = 0; j < 0x80; ) {
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printf("\n%2x", j);
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for (i = 0; i < 16; i++) {
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dm_i2c_read(dev, j + i, &val, 1);
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printf("\t%2x", val);
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}
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j += 0x10;
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}
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printf("\nEXT Page 1");
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val = PFUZE100_PAGE_REGISTER_PAGE1;
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if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
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puts("i2c write failed\n");
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return 0;
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}
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for (j = 0x80; j < 0x100; ) {
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printf("\n%2x", j);
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for (i = 0; i < 16; i++) {
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dm_i2c_read(dev, j + i, &val, 1);
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printf("\t%2x", val);
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}
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j += 0x10;
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}
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printf("\nEXT Page 2");
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val = PFUZE100_PAGE_REGISTER_PAGE2;
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if (dm_i2c_write(dev, PFUZE100_PAGE_REGISTER, &val, 1)) {
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puts("i2c write failed\n");
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return 0;
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}
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for (j = 0x80; j < 0x100; ) {
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printf("\n%2x", j);
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for (i = 0; i < 16; i++) {
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dm_i2c_read(dev, j + i, &val, 1);
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printf("\t%2x", val);
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}
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j += 0x10;
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}
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printf("\n");
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}
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#endif /* DEBUG */
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return programmed;
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}
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#ifndef CONFIG_SPL_BUILD
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static int pf0100_prog(void)
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{
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int rc;
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struct udevice *dev = NULL;
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unsigned char bus = 1;
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unsigned char val;
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unsigned int i;
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if (pmic_init() == 3) {
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puts("PMIC already programmed, exiting\n");
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return CMD_RET_FAILURE;
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}
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/* set up gpio to manipulate vprog, initially off */
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imx_iomux_v3_setup_multiple_pads(pmic_prog_pads,
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ARRAY_SIZE(pmic_prog_pads));
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gpio_direction_output(PMIC_PROG_VOLTAGE, 0);
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rc = i2c_get_chip_for_busnum(bus, PFUZE100_I2C_ADDR, 1, &dev);
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if (rc) {
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printf("failed to get device for PMIC at address 0x%x\n",
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PFUZE100_I2C_ADDR);
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return CMD_RET_FAILURE;
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}
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for (i = 0; i < ARRAY_SIZE(pmic_otp_prog); i++) {
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switch (pmic_otp_prog[i].cmd) {
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case pmic_i2c:
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val = (unsigned char) (pmic_otp_prog[i].value & 0xff);
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if (dm_i2c_write(dev, pmic_otp_prog[i].reg, &val, 1)) {
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printf("i2c write failed, reg 0x%2x, value 0x%2x\n",
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pmic_otp_prog[i].reg, val);
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return CMD_RET_FAILURE;
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}
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break;
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case pmic_delay:
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udelay(pmic_otp_prog[i].value * 1000);
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break;
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case pmic_vpgm:
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gpio_direction_output(PMIC_PROG_VOLTAGE,
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pmic_otp_prog[i].value);
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break;
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case pmic_pwr:
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/* TODO */
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break;
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}
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}
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return CMD_RET_SUCCESS;
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}
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static int do_pf0100_prog(struct cmd_tbl *cmdtp, int flag, int argc,
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char *const argv[])
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{
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int ret;
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puts("Programming PMIC OTP...");
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ret = pf0100_prog();
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if (ret == CMD_RET_SUCCESS)
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puts("done.\n");
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else
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puts("failed.\n");
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return ret;
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}
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U_BOOT_CMD(
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pf0100_otp_prog, 1, 0, do_pf0100_prog,
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"Program the OTP fuses on the PMIC PF0100",
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""
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);
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#endif /* CONFIG_SPL_BUILD */
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