mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-08 22:24:32 +00:00
20e442ab2d
The current macro is a misnomer since it does not declare a device directly. Instead, it declares driver_info record which U-Boot uses at runtime to create a device. The distinction seems somewhat minor most of the time, but is becomes quite confusing when we actually want to declare a device, with of-platdata. We are left trying to distinguish between a device which isn't actually device, and a device that is (perhaps an 'instance'?) It seems better to rename this macro to describe what it actually is. The macros is not widely used, since boards should use devicetree to declare devices. Rename it to U_BOOT_DRVINFO(), which indicates clearly that this is declaring a new driver_info record, not a device. Signed-off-by: Simon Glass <sjg@chromium.org>
171 lines
4 KiB
C
171 lines
4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*/
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#include <common.h>
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#include <dm.h>
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#include <net.h>
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#include <asm/io.h>
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#include <netdev.h>
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#include <fm_eth.h>
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#include <fsl_mdio.h>
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#include <malloc.h>
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#include <asm/types.h>
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#include <fsl_dtsec.h>
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#include <asm/arch/soc.h>
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#include <asm/arch-fsl-layerscape/config.h>
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#include <asm/arch-fsl-layerscape/immap_lsch2.h>
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#include <asm/arch/fsl_serdes.h>
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#include <linux/delay.h>
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#include <net/pfe_eth/pfe_eth.h>
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#include <dm/platform_data/pfe_dm_eth.h>
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#include <i2c.h>
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#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
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static inline void ls1012ardb_reset_phy(void)
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{
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#ifdef CONFIG_TARGET_LS1012ARDB
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/* Through reset IO expander reset both RGMII and SGMII PHYs */
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#ifdef CONFIG_DM_I2C
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struct udevice *dev;
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int ret;
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/*
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* The I2C IO-expander PCAL9555A is mouted on I2C1 bus(bus number is 0).
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*/
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ret = i2c_get_chip_for_busnum(0, I2C_MUX_IO2_ADDR,
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1, &dev);
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if (ret) {
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printf("%s: Cannot find udev for a bus %d\n", __func__,
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0);
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return;
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}
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/* Config port 0
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* - config pin IOXP_RST_ETH1_B and IOXP_RST_ETH2_B
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* are enabled as an output.
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*/
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dm_i2c_reg_write(dev, 6, __PHY_MASK);
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/*
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* Set port 0 output a value to reset ETH2 interface
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* - pin IOXP_RST_ETH2_B output 0b0
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*/
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dm_i2c_reg_write(dev, 2, __PHY_ETH2_MASK);
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mdelay(10);
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dm_i2c_reg_write(dev, 2, __PHY_ETH1_MASK);
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/*
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* Set port 0 output a value to reset ETH1 interface
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* - pin IOXP_RST_ETH1_B output 0b0
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*/
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mdelay(10);
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dm_i2c_reg_write(dev, 2, 0xFF);
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#else
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i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
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i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
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mdelay(10);
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i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH1_MASK);
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mdelay(10);
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i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
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#endif
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mdelay(50);
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#endif
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}
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int pfe_eth_board_init(struct udevice *dev)
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{
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static int init_done;
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struct mii_dev *bus;
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struct pfe_mdio_info mac_mdio_info;
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struct pfe_eth_dev *priv = dev_get_priv(dev);
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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int srds_s1 = in_be32(&gur->rcwsr[4]) &
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FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
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srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
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if (!init_done) {
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ls1012ardb_reset_phy();
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mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
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mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
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bus = pfe_mdio_init(&mac_mdio_info);
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if (!bus) {
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printf("Failed to register mdio\n");
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return -1;
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}
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init_done = 1;
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}
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pfe_set_mdio(priv->gemac_port,
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miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
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switch (srds_s1) {
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case 0x3508:
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if (!priv->gemac_port) {
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/* MAC1 */
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pfe_set_phy_address_mode(priv->gemac_port,
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CONFIG_PFE_EMAC1_PHY_ADDR,
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PHY_INTERFACE_MODE_SGMII);
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} else {
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/* MAC2 */
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pfe_set_phy_address_mode(priv->gemac_port,
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CONFIG_PFE_EMAC2_PHY_ADDR,
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PHY_INTERFACE_MODE_RGMII_ID);
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}
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break;
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case 0x2208:
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if (!priv->gemac_port) {
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/* MAC1 */
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pfe_set_phy_address_mode(priv->gemac_port,
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CONFIG_PFE_EMAC1_PHY_ADDR,
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PHY_INTERFACE_MODE_SGMII_2500);
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} else {
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/* MAC2 */
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pfe_set_phy_address_mode(priv->gemac_port,
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CONFIG_PFE_EMAC2_PHY_ADDR,
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PHY_INTERFACE_MODE_SGMII_2500);
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}
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break;
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default:
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printf("unsupported SerDes PRCTL= %d\n", srds_s1);
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break;
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}
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return 0;
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}
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static struct pfe_eth_pdata pfe_pdata0 = {
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.pfe_eth_pdata_mac = {
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.iobase = (phys_addr_t)EMAC1_BASE_ADDR,
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.phy_interface = 0,
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},
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.pfe_ddr_addr = {
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.ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
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.ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
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},
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};
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static struct pfe_eth_pdata pfe_pdata1 = {
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.pfe_eth_pdata_mac = {
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.iobase = (phys_addr_t)EMAC2_BASE_ADDR,
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.phy_interface = 1,
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},
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.pfe_ddr_addr = {
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.ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
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.ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
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},
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};
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U_BOOT_DRVINFO(ls1012a_pfe0) = {
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.name = "pfe_eth",
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.plat = &pfe_pdata0,
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};
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U_BOOT_DRVINFO(ls1012a_pfe1) = {
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.name = "pfe_eth",
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.plat = &pfe_pdata1,
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};
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