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https://github.com/AsahiLinux/u-boot
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765547dc5e
This patch adds MPC8569MDS board support. The UART, QE UEC1 and UEC2, BRD EEPROM on I2C2 bus, PCI express and DDR3 SPD are supported in this patch. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Hillel Avni <Hillel.Avni@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
59 lines
2.2 KiB
C
59 lines
2.2 KiB
C
/*
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* Copyright 2009 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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/*
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* LAW(Local Access Window) configuration:
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*
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*0) 0x0000_0000 0x7fff_ffff DDR 2G
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*1) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB
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*-) 0xe000_0000 0xe00f_ffff CCSR 1M
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*2) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M
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*3) 0xc000_0000 0xdfff_ffff SRIO 512MB
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*4.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB
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*4.b) 0xf800_0000 0xf800_7fff BCSR 32KB
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*4.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB
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*4.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB
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*4.e) 0xfe00_0000 0xffff_ffff Flash 32MB
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*
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*Notes:
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* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
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* If flash is 8M at default position (last 8M), no LAW needed.
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*
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*/
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struct law_entry law_table[] = {
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#ifndef CONFIG_SPD_EEPROM
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SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR),
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#endif
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SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
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SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
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SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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