mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-29 08:01:08 +00:00
2c597855aa
Copy the devicetree source for the H2+/H3/H5 SoCs and all existing boards from the Linux v5.18-rc1 tag. To maintain ABI compatibility with existing LTS kernels, one change moving some IP blocks to the r_intc interrupt controller is excluded. This effectively reverts Linux commits 994e5818392c and 9fdef3c3d8c2. This commit also adds the following new board devicetree: - sun8i-h3-nanopi-r1.dts This update should not impact any existing U-Boot functionality. Signed-off-by: Samuel Holland <samuel@sholland.org>
274 lines
6.5 KiB
Text
274 lines
6.5 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// Copyright (C) 2016 ARM Ltd.
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#include <sunxi-h3-h5.dtsi>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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#cooling-cells = <2>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <1>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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#cooling-cells = <2>;
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <2>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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#cooling-cells = <2>;
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <3>;
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enable-method = "psci";
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clocks = <&ccu CLK_CPUX>;
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clock-latency-ns = <244144>; /* 8 32k periods */
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#cooling-cells = <2>;
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};
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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arm,no-tick-in-suspend;
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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soc {
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syscon: system-control@1c00000 {
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compatible = "allwinner,sun50i-h5-system-control";
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reg = <0x01c00000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram_c1: sram@18000 {
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compatible = "mmio-sram";
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reg = <0x00018000 0x1c000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x00018000 0x1c000>;
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ve_sram: sram-section@0 {
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compatible = "allwinner,sun50i-h5-sram-c1",
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"allwinner,sun4i-a10-sram-c1";
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reg = <0x000000 0x1c000>;
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};
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};
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};
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video-codec@1c0e000 {
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compatible = "allwinner,sun50i-h5-video-engine";
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reg = <0x01c0e000 0x1000>;
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clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
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<&ccu CLK_DRAM_VE>;
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clock-names = "ahb", "mod", "ram";
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resets = <&ccu RST_BUS_VE>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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allwinner,sram = <&ve_sram 1>;
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};
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crypto: crypto@1c15000 {
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compatible = "allwinner,sun50i-h5-crypto";
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reg = <0x01c15000 0x1000>;
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
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clock-names = "bus", "mod";
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resets = <&ccu RST_BUS_CE>;
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};
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deinterlace: deinterlace@1e00000 {
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compatible = "allwinner,sun8i-h3-deinterlace";
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reg = <0x01e00000 0x20000>;
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clocks = <&ccu CLK_BUS_DEINTERLACE>,
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<&ccu CLK_DEINTERLACE>,
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<&ccu CLK_DRAM_DEINTERLACE>;
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clock-names = "bus", "mod", "ram";
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resets = <&ccu RST_BUS_DEINTERLACE>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&mbus 9>;
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interconnect-names = "dma-mem";
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};
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mali: gpu@1e80000 {
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compatible = "allwinner,sun50i-h5-mali", "arm,mali-450";
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reg = <0x01e80000 0x30000>;
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/*
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* While the datasheet lists an interrupt for the
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* PMU, the actual silicon does not have the PMU
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* block. Reads all return zero, and writes are
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* ignored.
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*/
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gp",
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"gpmmu",
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"pp",
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"pp0",
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"ppmmu0",
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"pp1",
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"ppmmu1",
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"pp2",
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"ppmmu2",
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"pp3",
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"ppmmu3";
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clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
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clock-names = "bus", "core";
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resets = <&ccu RST_BUS_GPU>;
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assigned-clocks = <&ccu CLK_GPU>;
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assigned-clock-rates = <384000000>;
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};
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ths: thermal-sensor@1c25000 {
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compatible = "allwinner,sun50i-h5-ths";
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reg = <0x01c25000 0x400>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&ccu RST_BUS_THS>;
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clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
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clock-names = "bus", "mod";
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nvmem-cells = <&ths_calibration>;
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nvmem-cell-names = "calibration";
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#thermal-sensor-cells = <1>;
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};
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};
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thermal-zones {
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cpu_thermal: cpu-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&ths 0>;
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trips {
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cpu_hot_trip: cpu-hot {
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temperature = <80000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_very_hot_trip: cpu-very-hot {
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temperature = <100000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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cooling-maps {
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cpu-hot-limit {
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trip = <&cpu_hot_trip>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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gpu-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&ths 1>;
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};
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};
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};
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&ccu {
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compatible = "allwinner,sun50i-h5-ccu";
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};
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&display_clocks {
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compatible = "allwinner,sun50i-h5-de2-clk";
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};
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&mbus {
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compatible = "allwinner,sun50i-h5-mbus";
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};
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&mmc0 {
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compatible = "allwinner,sun50i-h5-mmc",
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"allwinner,sun50i-a64-mmc";
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clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
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clock-names = "ahb", "mmc";
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};
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&mmc1 {
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compatible = "allwinner,sun50i-h5-mmc",
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"allwinner,sun50i-a64-mmc";
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clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
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clock-names = "ahb", "mmc";
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};
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&mmc2 {
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compatible = "allwinner,sun50i-h5-emmc",
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"allwinner,sun50i-a64-emmc";
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clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
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clock-names = "ahb", "mmc";
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};
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&pio {
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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compatible = "allwinner,sun50i-h5-pinctrl";
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};
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&rtc {
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compatible = "allwinner,sun50i-h5-rtc";
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};
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&sid {
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compatible = "allwinner,sun50i-h5-sid";
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};
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