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u-boot/board/freescale/ls1088a
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Tom Rini 450de19b80 ls1088a: Guard get_board_ddr_clk function correctly 
When we have CONFIG_DYNAMIC_DDR_CLK_FREQ set is the only time we should
have this function, so guard it so that we can include <clock_legacy.h>
in this file later on.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:18 -05:00
..
ddr.c WS cleanup: remove excessive empty lines 2021-09-30 08:08:56 -04:00
ddr.h armv8: ls1088: Update 1900MT/s DDR timing to bring consistency 2018-05-09 09:17:51 -05:00
eth_ls1088aqds.c dm: i2c: use CONFIG_IS_ENABLED macro for DM_I2C/DM_I2C_GPIO 2021-02-21 06:08:00 +01:00
eth_ls1088ardb.c net: replace the "xfi" phy-mode with "10gbase-r" 2021-09-28 18:50:56 +03:00
Kconfig board: Kconfig: Re-Arrangement of PPA firmware and header addresses 2018-06-08 16:43:19 -07:00
ls1088a.c ls1088a: Guard get_board_ddr_clk function correctly 2021-12-27 16:20:18 -05:00
ls1088a_qixis.h armv8: ls1088aqds: support DSPI mode by hwconfig 2019-08-22 09:07:36 +05:30
MAINTAINERS board: ls1088a: Update MAINTAINERS 2021-03-05 10:25:42 +05:30
Makefile SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
README net: replace the "xfi" phy-mode with "10gbase-r" 2021-09-28 18:50:56 +03:00

README 

Overview
--------
The LS1088A Reference Design (RDB) is a high-performance computing,
evaluation, and development platform that supports ARM SoC LS1088A and its
derivatives.


LS1088A SoC Overview
--------------------------------------
Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc

RDB Default Switch Settings (1: ON; 0: OFF)
-------------------------------------------

For QSPI Boot
SW1 0011 0001
SW2 x100 0000
SW3 1111 0010
SW4 1001 0011
SW5 1111 0000

For SD Boot
SW1 0010 0000
SW2 0100 0000
SW3 1111 0010
SW4 1001 0011
SW5 1111 0000

For eMMC Boot
SW1 0010 0000
SW2 1100 0000
SW3 1111 0010
SW4 1001 0011
SW5 1111 0000

Alternately you can use this command to switch from QSPI to SD

=> i2c mw 66 0x60 0x20; i2c mw 66 10 10;i2c mw 66 10 21

 LS1088ARDB board Overview
 -------------------------
 - SERDES Connections, 16 lanes supporting:
      - PCI Express - 3.0
      - SATA 3.0
      - 10GBase-R
      - QSGMII
 - DDR Controller
     - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four
       chip-selects on one DIMM connector. Support is up to 2133MT/s, Although MAX default
       with FSL refernce software is 2100MT/s
 - 2 QSPI-NOR Spansion(S25FS512SDSMFI011) flash of size 64MB
 - IFC/Local Bus
    - One 2 GB NAND flash with ECC support, not as boot source
    - CPLD of size 2K
 - USB 3.0
    - Two high speed USB 3.0 ports
    - First USB 3.0 port configured as Host with Type-A connector
    - Second USB 3.0 port configured as OTG with micro-AB connector
 - SDHC/eMMC
    - SDHC slot and onboard eMMC are muxed together
 - 4 I2C controllers
 - Two SATA onboard connectors
 - 2 UART
 - JTAG support
 - QSPI emulator support
 - TDM riser support

QDS Default Switch Settings (1: ON; 0: OFF)
-------------------------------------------

For 16b IFC-NOR
SW1 0001 0010
SW2 x110 1111

For QSPI Boot
SW1 0011 0001
SW2 0110 1111

For SD Boot
SW1 0010 0000
SW2 0110 1111

For eMMC Boot
SW1 0010 0000
SW2 1110 1111

For I2C (ext. addr.)
SW1 0010 0100
SW2 1110 1111

SW3 to SW12 are identical for all boot source

SW3 0010 0100
SW4 0010 0000
SW5 1110 0111
SW6 1110 1000
SW7 0001 1101
SW8 0000 1101
SW9 1100 1010
SW10 1110 1000
SW11 1111 0100
SW12 1111 1111

 LS1088AQDS board Overview
 -------------------------
 - SERDES Connections, 16 lanes supporting:
      - PCI Express - 3.0
      - SATA 3.0
      - 2 10GBase-R
      - QSGMII, SGMII with help for Riser card
      - 2 RGMII
      - 5 slot for Riser card or PCIe NIC
 - DDR Controller
     - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four
       chip-selects on one DIMM connector. Support is up to 2133MT/s, Although MAX default
       with FSL refernce software is 2100MT/s
 - 2 QSPI-NOR Spansion(S25FS512SDSMFI011) flash of size 64MB
 - IFC/Local Bus
    - One 2 GB NAND flash with ECC support, not as boot source
    - CPLD of size 2K
 - USB 3.0
    - Two high speed USB 3.0 ports
    - First USB 3.0 port configured as Host with Type-A connector
    - Second USB 3.0 port configured as OTG with micro-AB connector
 - SDHC/eMMC
    - SDHC/eMMC slot via adaptor
 - 4 I2C controllers
 - Two SATA onboard connectors
 - 2 UART
 - JTAG support
 - DSPI
 - PROMJET support
 - QSPI emulator support
 - TDM riser support

QSPI flash memory map valid for both QDS and RDB
  Image                               Flash Offset
 RCW+PBI                             0x00000000
 Boot firmware (U-Boot)              0x00100000
 Boot firmware Environment           0x00300000
 PPA firmware                        0x00400000
 DPAA2 MC                            0x00A00000
 DPAA2 DPL                           0x00D00000
 DPAA2 DPC                           0x00E00000
 Kernel.itb                          0x01000000