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https://github.com/AsahiLinux/u-boot
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
189 lines
5.1 KiB
ArmAsm
189 lines
5.1 KiB
ArmAsm
/*
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* lowlevel_init.S - basic hardware initialization for the KS8695 CPU
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*
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* Copyright (c) 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/arch/platform.h>
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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/*
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*************************************************************************
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*
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* Handy dandy macros
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*
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*************************************************************************
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*/
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/* Delay a bit */
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.macro DELAY_FOR cycles, reg0
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ldr \reg0, =\cycles
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subs \reg0, \reg0, #1
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subne pc, pc, #0xc
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.endm
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/*
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*************************************************************************
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*
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* Some local storage.
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*
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*************************************************************************
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*/
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/* Should we boot with an interactive console or not */
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.globl serial_console
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/*
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*************************************************************************
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*
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* Raw hardware initialization code. The important thing is to get
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* SDRAM setup and running. We do some other basic things here too,
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* like getting the PLL set for high speed, and init the LEDs.
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*
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*************************************************************************
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*/
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.globl lowlevel_init
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lowlevel_init:
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#if DEBUG
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/*
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* enable UART for early debug trace
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*/
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ldr r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR)
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mov r2, #((25000000+CONFIG_BAUDRATE/2) / CONFIG_BAUDRATE)
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str r2, [r1]
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ldr r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL)
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mov r2, #KS8695_UART_LINEC_WLEN8
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str r2, [r1] /* 8 data bits, no parity, 1 stop */
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ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
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mov r2, #0x41
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str r2, [r1] /* write 'A' */
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#endif
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#if DEBUG
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ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
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mov r2, #0x42
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str r2, [r1]
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#endif
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/*
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* remap the memory and flash regions. we want to end up with
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* ram from address 0, and flash at 32MB.
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*/
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ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL0)
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ldr r2, =0xbfc00040
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str r2, [r1] /* large flash map */
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ldr pc, =(highflash+0x02000000-0x00f00000) /* jump to high flash address */
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highflash:
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ldr r2, =0x8fe00040
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str r2, [r1] /* remap flash range */
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/*
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* remap the second select region to the 4MB immediately after
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* the first region. This way if you have a larger flash (say 8Mb)
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* then you can have it all mapped nicely. Has no effect if you
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* only have a 4Mb or smaller flash.
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*/
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ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL1)
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ldr r2, =0x9fe40040
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str r2, [r1] /* remap flash2 region, contiguous */
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ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
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ldr r2, =0x30000005
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str r2, [r1] /* enable both flash selects */
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#ifdef CONFIG_CM41xx
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/*
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* map the second flash chip, using the external IO lines.
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*/
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ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL0)
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ldr r2, =0xafe80b6d
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str r2, [r1] /* remap io0 region, contiguous */
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ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL1)
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ldr r2, =0xbfec0b6d
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str r2, [r1] /* remap io1 region, contiguous */
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ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL)
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ldr r2, =0x30050005
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str r2, [r1] /* enable second flash */
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#endif
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/*
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* before relocating, we have to setup RAM timing
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*/
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ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0)
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#if (PHYS_SDRAM_1_SIZE == 0x02000000)
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ldr r2, =0x7fc0000e /* 32MB */
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#else
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ldr r2, =0x3fc0000e /* 16MB */
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#endif
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str r2, [r1] /* configure sdram bank0 setup */
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ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1)
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mov r2, #0
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str r2, [r1] /* configure sdram bank1 setup */
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ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL)
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ldr r2, =0x0000000a
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str r2, [r1] /* set RAS/CAS timing */
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ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
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ldr r2, =0x00030000
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str r2, [r1] /* send NOP command */
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DELAY_FOR 0x100, r0
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ldr r2, =0x00010000
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str r2, [r1] /* send PRECHARGE-ALL */
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DELAY_FOR 0x100, r0
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ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_REFRESH)
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ldr r2, =0x00000020
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str r2, [r1] /* set for fast refresh */
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DELAY_FOR 0x100, r0
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ldr r2, =0x00000190
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str r2, [r1] /* set normal refresh timing */
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ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
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ldr r2, =0x00020033
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str r2, [r1] /* send mode command */
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DELAY_FOR 0x100, r0
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ldr r2, =0x01f00000
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str r2, [r1] /* enable sdram fifos */
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/*
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* set pll to top speed
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*/
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ldr r1, =(KS8695_IO_BASE+KS8695_SYSTEN_BUS_CLOCK)
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mov r2, #0
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str r2, [r1] /* set pll clock to 166MHz */
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ldr r1, =(KS8695_IO_BASE+KS8695_SWITCH_CTRL0)
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ldr r2, [r1] /* Get switch ctrl0 register */
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and r2, r2, #0x0fc00000 /* Mask out LED control bits */
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orr r2, r2, #0x01800000 /* Set Link/activity/speed actions */
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str r2, [r1]
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#ifdef CONFIG_CM4008
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ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_MODE)
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ldr r2, =0x0000fe30
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str r2, [r1] /* enable LED's as outputs */
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ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_DATA)
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ldr r2, =0x0000fe20
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str r2, [r1] /* turn on power LED */
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#endif
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#if defined(CONFIG_CM4008) || defined(CONFIG_CM41xx)
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ldr r2, [r1] /* get current GPIO input data */
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tst r2, #0x8 /* check if "erase" depressed */
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beq nobutton
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mov r2, #0 /* be quiet on boot, no console */
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ldr r1, =serial_console
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str r2, [r1]
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nobutton:
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#endif
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add lr, lr, #0x02000000 /* flash is now mapped high */
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add ip, ip, #0x02000000 /* this is a hack */
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mov pc, lr /* all done, return */
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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