mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-21 02:33:07 +00:00
786f888b74
Offsets are described in the datasheet at section:
"11.4.4.2 NAND Flash Boot: PMECC Error Detection and Correction".
For testing I "injected" bit flips into u-boot NAND memory area,
and then read back. PMECC could not correct the errors. With the
offsets updated everything is fine.
Fixes: 3225f34e5c ("ARM: atmel: add sama5d3xek support")
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
208 lines
7 KiB
C
208 lines
7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Chip-specific header file for the SAMA5D3 family
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*
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* (C) 2012 - 2013 Atmel Corporation.
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* Bo Shen <voice.shen@atmel.com>
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*
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* Definitions for the SoC:
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* SAMA5D3
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*/
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#ifndef SAMA5D3_H
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#define SAMA5D3_H
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/*
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* Peripheral identifiers/interrupts.
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*/
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#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
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#define ATMEL_ID_SYS 1 /* System Controller Interrupt */
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#define ATMEL_ID_DBGU 2 /* Debug Unit Interrupt */
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#define ATMEL_ID_PIT 3 /* Periodic Interval Timer Interrupt */
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#define ATMEL_ID_WDT 4 /* Watchdog timer Interrupt */
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#define ATMEL_ID_SMC 5 /* Multi-bit ECC Interrupt */
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#define ATMEL_ID_PIOA 6 /* Parallel I/O Controller A */
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#define ATMEL_ID_PIOB 7 /* Parallel I/O Controller B */
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#define ATMEL_ID_PIOC 8 /* Parallel I/O Controller C */
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#define ATMEL_ID_PIOD 9 /* Parallel I/O Controller D */
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#define ATMEL_ID_PIOE 10 /* Parallel I/O Controller E */
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#define ATMEL_ID_SMD 11 /* SMD Soft Modem */
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#define ATMEL_ID_USART0 12 /* USART 0 */
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#define ATMEL_ID_USART1 13 /* USART 1 */
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#define ATMEL_ID_USART2 14 /* USART 2 */
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#define ATMEL_ID_USART3 15 /* USART 3 */
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#define ATMEL_ID_UART0 16
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#define ATMEL_ID_UART1 17
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#define ATMEL_ID_TWI0 18 /* Two-Wire Interface 0 */
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#define ATMEL_ID_TWI1 19 /* Two-Wire Interface 1 */
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#define ATMEL_ID_TWI2 20 /* Two-Wire Interface 2 */
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#define ATMEL_ID_MCI0 21 /* High Speed Multimedia Card Interface 0 */
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#define ATMEL_ID_MCI1 22 /* */
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#define ATMEL_ID_MCI2 23 /* */
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#define ATMEL_ID_SPI0 24 /* Serial Peripheral Interface 0 */
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#define ATMEL_ID_SPI1 25 /* Serial Peripheral Interface 1 */
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#define ATMEL_ID_TC0 26 /* */
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#define ATMEL_ID_TC1 27 /* */
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#define ATMEL_ID_PWMC 28 /* Pulse Width Modulation Controller */
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#define ATMEL_ID_TSC 29 /* Touch Screen ADC Controller */
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#define ATMEL_ID_DMA0 30 /* DMA Controller */
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#define ATMEL_ID_DMA1 31 /* DMA Controller */
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#define ATMEL_ID_UHPHS 32 /* USB Host High Speed */
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#define ATMEL_ID_UDPHS 33 /* USB Device High Speed */
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#define ATMEL_ID_GMAC 34
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#define ATMEL_ID_EMAC 35 /* Ethernet MAC */
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#define ATMEL_ID_LCDC 36 /* LCD Controller */
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#define ATMEL_ID_ISI 37 /* Image Sensor Interface */
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#define ATMEL_ID_SSC0 38 /* Synchronous Serial Controller 0 */
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#define ATMEL_ID_SSC1 39 /* Synchronous Serial Controller 1 */
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#define ATMEL_ID_CAN0 40
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#define ATMEL_ID_CAN1 41
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#define ATMEL_ID_SHA 42
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#define ATMEL_ID_AES 43
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#define ATMEL_ID_TDES 44
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#define ATMEL_ID_TRNG 45
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#define ATMEL_ID_ARM 46
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#define ATMEL_ID_IRQ0 47 /* Advanced Interrupt Controller */
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#define ATMEL_ID_FUSE 48
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#define ATMEL_ID_MPDDRC 49
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/* sama5d3 series chip id definitions */
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#define ARCH_ID_SAMA5D3 0x8a5c07c0
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#define ARCH_EXID_SAMA5D31 0x00444300
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#define ARCH_EXID_SAMA5D33 0x00414300
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#define ARCH_EXID_SAMA5D34 0x00414301
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#define ARCH_EXID_SAMA5D35 0x00584300
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#define ARCH_EXID_SAMA5D36 0x00004301
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#define cpu_is_sama5d3() (get_chip_id() == ARCH_ID_SAMA5D3)
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#define cpu_is_sama5d31() (cpu_is_sama5d3() && \
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(get_extension_chip_id() == ARCH_EXID_SAMA5D31))
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#define cpu_is_sama5d33() (cpu_is_sama5d3() && \
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(get_extension_chip_id() == ARCH_EXID_SAMA5D33))
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#define cpu_is_sama5d34() (cpu_is_sama5d3() && \
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(get_extension_chip_id() == ARCH_EXID_SAMA5D34))
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#define cpu_is_sama5d35() (cpu_is_sama5d3() && \
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(get_extension_chip_id() == ARCH_EXID_SAMA5D35))
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#define cpu_is_sama5d36() (cpu_is_sama5d3() && \
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(get_extension_chip_id() == ARCH_EXID_SAMA5D36))
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/*
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* User Peripherals physical base addresses.
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*/
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#define ATMEL_BASE_MCI0 0xf0000000
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#define ATMEL_BASE_SPI0 0xf0004000
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#define ATMEL_BASE_SSC0 0xf000C000
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#define ATMEL_BASE_TC2 0xf0010000
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#define ATMEL_BASE_TWI0 0xf0014000
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#define ATMEL_BASE_TWI1 0xf0018000
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#define ATMEL_BASE_USART0 0xf001c000
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#define ATMEL_BASE_USART1 0xf0020000
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#define ATMEL_BASE_UART0 0xf0024000
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#define ATMEL_BASE_GMAC 0xf0028000
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#define ATMEL_BASE_PWMC 0xf002c000
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#define ATMEL_BASE_LCDC 0xf0030000
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#define ATMEL_BASE_ISI 0xf0034000
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#define ATMEL_BASE_SFR 0xf0038000
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/* Reserved: 0xf003c000 - 0xf8000000 */
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#define ATMEL_BASE_MCI1 0xf8000000
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#define ATMEL_BASE_MCI2 0xf8004000
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#define ATMEL_BASE_SPI1 0xf8008000
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#define ATMEL_BASE_SSC1 0xf800c000
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#define ATMEL_BASE_CAN1 0xf8010000
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#define ATMEL_BASE_TC3 0xf8014000
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#define ATMEL_BASE_TSADC 0xf8018000
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#define ATMEL_BASE_TWI2 0xf801c000
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#define ATMEL_BASE_USART2 0xf8020000
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#define ATMEL_BASE_USART3 0xf8024000
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#define ATMEL_BASE_UART1 0xf8028000
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#define ATMEL_BASE_EMAC 0xf802c000
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#define ATMEL_BASE_UDPHS 0xf8030000
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#define ATMEL_BASE_SHA 0xf8034000
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#define ATMEL_BASE_AES 0xf8038000
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#define ATMEL_BASE_TDES 0xf803c000
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#define ATMEL_BASE_TRNG 0xf8040000
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/* Reserved: 0xf804400 - 0xffffc00 */
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/*
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* System Peripherals physical base addresses.
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*/
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#define ATMEL_BASE_SYS 0xffffc000
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#define ATMEL_BASE_SMC 0xffffc000
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#define ATMEL_BASE_PMECC (ATMEL_BASE_SMC + 0x070)
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#define ATMEL_BASE_PMERRLOC (ATMEL_BASE_SMC + 0x500)
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#define ATMEL_BASE_FUSE 0xffffe400
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#define ATMEL_BASE_DMAC0 0xffffe600
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#define ATMEL_BASE_DMAC1 0xffffe800
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#define ATMEL_BASE_MPDDRC 0xffffea00
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#define ATMEL_BASE_MATRIX 0xffffec00
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#define ATMEL_BASE_DBGU 0xffffee00
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#define ATMEL_BASE_AIC 0xfffff000
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#define ATMEL_BASE_PIOA 0xfffff200
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#define ATMEL_BASE_PIOB 0xfffff400
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#define ATMEL_BASE_PIOC 0xfffff600
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#define ATMEL_BASE_PIOD 0xfffff800
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#define ATMEL_BASE_PIOE 0xfffffa00
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#define ATMEL_BASE_PMC 0xfffffc00
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#define ATMEL_BASE_RSTC 0xfffffe00
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#define ATMEL_BASE_SHDWN 0xfffffe10
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#define ATMEL_BASE_PIT 0xfffffe30
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#define ATMEL_BASE_WDT 0xfffffe40
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#define ATMEL_BASE_SCKCR 0xfffffe50
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#define ATMEL_BASE_GPBR 0xfffffe60
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#define ATMEL_BASE_RTC 0xfffffeb0
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/* Reserved: 0xfffffee0 - 0xffffffff */
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#define ATMEL_CHIPID_CIDR 0xffffee40
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#define ATMEL_CHIPID_EXID 0xffffee44
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/*
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* Internal Memory.
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*/
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#define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */
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#define ATMEL_BASE_SRAM 0x00200000 /* Internal ROM base address */
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#define ATMEL_BASE_SRAM0 0x00300000 /* Internal SRAM base address */
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#define ATMEL_BASE_SRAM1 0x00310000 /* Internal SRAM base address */
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#define ATMEL_BASE_SMD 0x00400000 /* Internal ROM base address */
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#define ATMEL_BASE_UDPHS_FIFO 0x00500000 /* USB Device HS controller */
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#define ATMEL_BASE_OHCI 0x00600000 /* USB Host controller (OHCI) */
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#define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */
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#define ATMEL_BASE_AXI 0x00800000 /* Video Decoder Controller */
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#define ATMEL_BASE_DAP 0x00900000 /* Video Decoder Controller */
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/*
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* External memory
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*/
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#define ATMEL_BASE_CS0 0x10000000
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#define ATMEL_BASE_DDRCS 0x20000000
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#define ATMEL_BASE_CS1 0x40000000
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#define ATMEL_BASE_CS2 0x50000000
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#define ATMEL_BASE_CS3 0x60000000
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/*
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* Other misc defines
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*/
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#define ATMEL_PIO_PORTS 5
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#define CPU_HAS_PCR
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/* Timer */
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#define CONFIG_SYS_TIMER_COUNTER 0xfffffe3c
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/*
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* PMECC table in ROM
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*/
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#define ATMEL_PMECC_INDEX_OFFSET_512 0x8000
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#define ATMEL_PMECC_INDEX_OFFSET_1024 0x10000
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/*
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* SAMA5D3 specific prototypes
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*/
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#ifndef __ASSEMBLY__
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unsigned int get_chip_id(void);
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unsigned int get_extension_chip_id(void);
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unsigned int has_emac(void);
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unsigned int has_gmac(void);
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unsigned int has_lcdc(void);
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char *get_cpu_name(void);
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#endif
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#endif
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