mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-21 02:33:07 +00:00
54bd9ddf21
Sync dts from Linux Kernel
commit f838f8d2b694cf9d524dc("mfd: ab8500-debugfs: Remove extraneous seq_putc")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
614 lines
13 KiB
Text
614 lines
13 KiB
Text
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright 2017 NXP
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* Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
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*/
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/dts-v1/;
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#include "imx8mq.dtsi"
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/ {
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model = "NXP i.MX8MQ EVK";
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compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
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chosen {
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stdout-path = &uart1;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x00000000 0x40000000 0 0xc0000000>;
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};
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pcie0_refclk: pcie0-refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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};
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reg_usdhc2_vmmc: regulator-vsd-3v3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2>;
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compatible = "regulator-fixed";
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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buck2_reg: regulator-buck2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_buck2>;
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compatible = "regulator-gpio";
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regulator-name = "vdd_arm";
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1000000>;
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gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
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states = <1000000 0x0
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900000 0x1>;
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regulator-boot-on;
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regulator-always-on;
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};
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ir-receiver {
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compatible = "gpio-ir-receiver";
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gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ir>;
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linux,autosuspend-period = <125>;
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};
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wm8524: audio-codec {
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#sound-dai-cells = <0>;
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compatible = "wlf,wm8524";
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wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
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};
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sound-wm8524 {
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compatible = "simple-audio-card";
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simple-audio-card,name = "wm8524-audio";
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simple-audio-card,format = "i2s";
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simple-audio-card,frame-master = <&cpudai>;
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simple-audio-card,bitclock-master = <&cpudai>;
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simple-audio-card,widgets =
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"Line", "Left Line Out Jack",
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"Line", "Right Line Out Jack";
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simple-audio-card,routing =
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"Left Line Out Jack", "LINEVOUTL",
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"Right Line Out Jack", "LINEVOUTR";
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cpudai: simple-audio-card,cpu {
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sound-dai = <&sai2>;
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};
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link_codec: simple-audio-card,codec {
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sound-dai = <&wm8524>;
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clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
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};
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};
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sound-spdif {
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compatible = "fsl,imx-audio-spdif";
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model = "imx-spdif";
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spdif-controller = <&spdif1>;
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spdif-out;
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spdif-in;
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};
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sound-hdmi-arc {
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compatible = "fsl,imx-audio-spdif";
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model = "imx-hdmi-arc";
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spdif-controller = <&spdif2>;
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spdif-in;
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};
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};
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&A53_0 {
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cpu-supply = <&buck2_reg>;
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};
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&A53_1 {
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cpu-supply = <&buck2_reg>;
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};
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&A53_2 {
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cpu-supply = <&buck2_reg>;
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};
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&A53_3 {
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cpu-supply = <&buck2_reg>;
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};
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&ddrc {
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operating-points-v2 = <&ddrc_opp_table>;
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ddrc_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-25M {
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opp-hz = /bits/ 64 <25000000>;
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};
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opp-100M {
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opp-hz = /bits/ 64 <100000000>;
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};
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/*
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* On imx8mq B0 PLL can't be bypassed so low bus is 166M
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*/
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opp-166M {
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opp-hz = /bits/ 64 <166935483>;
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};
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opp-800M {
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opp-hz = /bits/ 64 <800000000>;
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};
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};
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};
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&dphy {
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status = "okay";
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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};
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};
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};
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&gpio5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wifi_reset>;
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wl-reg-on-hog {
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gpio-hog;
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gpios = <29 GPIO_ACTIVE_HIGH>;
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output-high;
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pmic@8 {
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compatible = "fsl,pfuze100";
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reg = <0x8>;
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regulators {
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sw1a_reg: sw1ab {
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regulator-min-microvolt = <825000>;
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regulator-max-microvolt = <1100000>;
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};
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sw1c_reg: sw1c {
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regulator-min-microvolt = <825000>;
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regulator-max-microvolt = <1100000>;
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};
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sw2_reg: sw2 {
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1100000>;
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regulator-always-on;
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};
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sw3a_reg: sw3ab {
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regulator-min-microvolt = <825000>;
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regulator-max-microvolt = <1100000>;
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regulator-always-on;
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};
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sw4_reg: sw4 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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swbst_reg: swbst {
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5150000>;
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};
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snvs_reg: vsnvs {
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <3000000>;
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regulator-always-on;
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};
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vref_reg: vrefddr {
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regulator-always-on;
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};
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vgen1_reg: vgen1 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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};
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vgen2_reg: vgen2 {
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <975000>;
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regulator-always-on;
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};
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vgen3_reg: vgen3 {
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regulator-min-microvolt = <1675000>;
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regulator-max-microvolt = <1975000>;
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regulator-always-on;
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};
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vgen4_reg: vgen4 {
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regulator-min-microvolt = <1625000>;
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regulator-max-microvolt = <1875000>;
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regulator-always-on;
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};
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vgen5_reg: vgen5 {
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regulator-min-microvolt = <3075000>;
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regulator-max-microvolt = <3625000>;
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regulator-always-on;
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};
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vgen6_reg: vgen6 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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};
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};
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&lcdif {
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status = "okay";
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};
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&mipi_dsi {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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panel@0 {
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pinctrl-0 = <&pinctrl_mipi_dsi>;
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pinctrl-names = "default";
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compatible = "raydium,rm67191";
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reg = <0>;
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reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
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dsi-lanes = <4>;
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port {
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panel_in: endpoint {
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remote-endpoint = <&mipi_dsi_out>;
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};
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};
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};
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ports {
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port@1 {
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reg = <1>;
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mipi_dsi_out: endpoint {
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remote-endpoint = <&panel_in>;
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};
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};
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};
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};
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&pcie0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie0>;
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reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
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clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
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<&clk IMX8MQ_CLK_PCIE1_AUX>,
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<&clk IMX8MQ_CLK_PCIE1_PHY>,
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<&pcie0_refclk>;
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clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
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status = "okay";
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};
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&pgc_gpu {
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power-supply = <&sw1a_reg>;
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};
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&qspi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi>;
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status = "okay";
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n25q256a: flash@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,n25q256a", "jedec,spi-nor";
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spi-max-frequency = <29000000>;
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};
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};
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&sai2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai2>;
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assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
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assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
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assigned-clock-rates = <0>, <24576000>;
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status = "okay";
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};
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&snvs_pwrkey {
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status = "okay";
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};
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&spdif1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spdif1>;
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assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>;
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assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
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assigned-clock-rates = <24576000>;
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status = "okay";
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};
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&spdif2 {
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assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>;
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assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
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assigned-clock-rates = <24576000>;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&usb3_phy1 {
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status = "okay";
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};
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&usb_dwc3_1 {
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dr_mode = "host";
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status = "okay";
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};
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&usdhc1 {
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assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
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assigned-clock-rates = <400000000>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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vqmmc-supply = <&sw4_reg>;
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bus-width = <8>;
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non-removable;
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no-sd;
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no-sdio;
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status = "okay";
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};
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&usdhc2 {
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assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
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assigned-clock-rates = <200000000>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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vmmc-supply = <®_usdhc2_vmmc>;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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status = "okay";
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};
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&iomuxc {
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pinctrl_buck2: vddarmgrp {
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fsl,pins = <
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MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
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>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
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MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
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MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
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MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
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MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
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MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
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MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
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MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
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MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
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MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
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MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
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MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
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MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
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MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
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MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
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MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
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>;
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};
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pinctrl_ir: irgrp {
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fsl,pins = <
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MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f
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>;
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};
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pinctrl_mipi_dsi: mipidsigrp {
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fsl,pins = <
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MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16
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>;
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};
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pinctrl_pcie0: pcie0grp {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
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MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
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>;
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};
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pinctrl_qspi: qspigrp {
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fsl,pins = <
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MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
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MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
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MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
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MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
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MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
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MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
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>;
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};
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pinctrl_reg_usdhc2: regusdhc2gpiogrp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
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>;
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};
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pinctrl_sai2: sai2grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
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MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
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MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
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MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
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MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
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>;
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};
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pinctrl_spdif1: spdif1grp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
|
|
MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
|
|
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1: usdhc1grp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
|
|
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
|
|
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
|
|
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
|
|
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
|
|
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
|
|
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
|
|
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
|
|
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
|
|
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
|
|
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
|
|
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_100mhz: usdhc1-100grp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
|
|
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
|
|
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
|
|
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
|
|
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
|
|
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
|
|
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
|
|
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
|
|
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
|
|
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
|
|
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
|
|
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_200mhz: usdhc1-200grp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
|
|
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
|
|
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
|
|
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
|
|
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
|
|
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
|
|
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
|
|
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
|
|
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
|
|
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
|
|
MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
|
|
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
|
|
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
|
|
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
|
|
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
|
|
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
|
|
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
|
|
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_100mhz: usdhc2-100grp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
|
|
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
|
|
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
|
|
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
|
|
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
|
|
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
|
|
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_200mhz: usdhc2-200grp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
|
|
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
|
|
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
|
|
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
|
|
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
|
|
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
|
|
MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_wdog: wdog1grp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
|
>;
|
|
};
|
|
|
|
pinctrl_wifi_reset: wifiresetgrp {
|
|
fsl,pins = <
|
|
MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16
|
|
>;
|
|
};
|
|
};
|