mirror of
https://github.com/AsahiLinux/u-boot
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c661c511e9
Add initial support PHYTEC phyCORE-i.MX8MP SOM.
Supported features:
- 2GB LPDDR4 RAM
- eMMC
- external SD
- debug UART2
- watchdog
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
161 lines
3.6 KiB
Text
161 lines
3.6 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 PHYTEC Messtechnik GmbH
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* Author: Teresa Remmet <t.remmet@phytec.de>
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*/
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/dts-v1/;
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#include <dt-bindings/leds/leds-pca9532.h>
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#include <dt-bindings/pwm/pwm.h>
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#include "imx8mp-phycore-som.dtsi"
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/ {
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model = "PHYTEC phyBOARD-Pollux i.MX8MP";
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compatible = "phytec,imx8mp-phyboard-pollux-rdk",
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"phytec,imx8mp-phycore-som", "fsl,imx8mp";
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chosen {
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stdout-path = &uart2;
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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startup-delay-us = <100>;
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off-on-delay-us = <12000>;
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};
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};
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&i2c2 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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pinctrl-1 = <&pinctrl_i2c2_gpio>;
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sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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eeprom@51 {
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compatible = "atmel,24c02";
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reg = <0x51>;
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pagesize = <16>;
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};
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leds@62 {
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compatible = "nxp,pca9533";
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reg = <0x62>;
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led1 {
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type = <PCA9532_TYPE_LED>;
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};
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led2 {
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type = <PCA9532_TYPE_LED>;
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};
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led3 {
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type = <PCA9532_TYPE_LED>;
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};
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};
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};
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&snvs_pwrkey {
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status = "okay";
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};
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/* debug console */
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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/* SD-Card */
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>;
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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vmmc-supply = <®_usdhc2_vmmc>;
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bus-width = <4>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
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MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
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>;
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};
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pinctrl_i2c2_gpio: i2c2gpiogrp {
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fsl,pins = <
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MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e3
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MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e3
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>;
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};
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pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
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MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
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>;
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};
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pinctrl_usdhc2_pins: usdhc2-gpiogrp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
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MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
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MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
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MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
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MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
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MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
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MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
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MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
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MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
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MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
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MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
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MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
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MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
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MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
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MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
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MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
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MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
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MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
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MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
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>;
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};
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};
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