mirror of
https://github.com/AsahiLinux/u-boot
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29caf9305b
Globally replace all occurances of WATCHDOG_RESET() with schedule(), which handles the HW_WATCHDOG functionality and the cyclic infrastructure. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
121 lines
2.6 KiB
C
121 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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#include <common.h>
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#include <cpu_func.h>
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/*
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* CPU test
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*
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* This test checks the arithmetic logic unit (ALU) of CPU.
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* It tests independently various groups of instructions using
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* run-time modification of the code to reduce the memory footprint.
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* For more details refer to post/cpu/ *.c files.
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*/
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#include <watchdog.h>
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#include <post.h>
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#include <asm/mmu.h>
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#if CONFIG_POST & CONFIG_SYS_POST_CPU
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extern int cpu_post_test_cmp (void);
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extern int cpu_post_test_cmpi (void);
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extern int cpu_post_test_two (void);
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extern int cpu_post_test_twox (void);
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extern int cpu_post_test_three (void);
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extern int cpu_post_test_threex (void);
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extern int cpu_post_test_threei (void);
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extern int cpu_post_test_andi (void);
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extern int cpu_post_test_srawi (void);
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extern int cpu_post_test_rlwnm (void);
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extern int cpu_post_test_rlwinm (void);
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extern int cpu_post_test_rlwimi (void);
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extern int cpu_post_test_store (void);
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extern int cpu_post_test_load (void);
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extern int cpu_post_test_cr (void);
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extern int cpu_post_test_b (void);
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extern int cpu_post_test_multi (void);
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extern int cpu_post_test_string (void);
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extern int cpu_post_test_complex (void);
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ulong cpu_post_makecr (long v)
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{
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ulong cr = 0;
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if (v < 0)
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cr |= 0x80000000;
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if (v > 0)
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cr |= 0x40000000;
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if (v == 0)
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cr |= 0x20000000;
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return cr;
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}
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int cpu_post_test (int flags)
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{
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int ic = icache_status();
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int ret = 0;
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schedule();
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if (ic)
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icache_disable();
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if (ret == 0)
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ret = cpu_post_test_cmp ();
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if (ret == 0)
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ret = cpu_post_test_cmpi ();
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if (ret == 0)
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ret = cpu_post_test_two ();
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if (ret == 0)
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ret = cpu_post_test_twox ();
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schedule();
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if (ret == 0)
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ret = cpu_post_test_three ();
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if (ret == 0)
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ret = cpu_post_test_threex ();
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if (ret == 0)
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ret = cpu_post_test_threei ();
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if (ret == 0)
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ret = cpu_post_test_andi ();
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schedule();
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if (ret == 0)
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ret = cpu_post_test_srawi ();
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if (ret == 0)
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ret = cpu_post_test_rlwnm ();
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if (ret == 0)
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ret = cpu_post_test_rlwinm ();
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if (ret == 0)
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ret = cpu_post_test_rlwimi ();
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schedule();
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if (ret == 0)
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ret = cpu_post_test_store ();
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if (ret == 0)
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ret = cpu_post_test_load ();
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if (ret == 0)
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ret = cpu_post_test_cr ();
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if (ret == 0)
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ret = cpu_post_test_b ();
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schedule();
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if (ret == 0)
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ret = cpu_post_test_multi ();
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schedule();
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if (ret == 0)
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ret = cpu_post_test_string ();
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if (ret == 0)
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ret = cpu_post_test_complex ();
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schedule();
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if (ic)
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icache_enable();
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schedule();
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return ret;
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}
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#endif /* CONFIG_POST & CONFIG_SYS_POST_CPU */
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