mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
4549e789c1
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have multiple licenses (in these cases, dual license) declared in the SPDX-License-Identifier tag. In this case we change from listing "LICENSE-A LICENSE-B" or "LICENSE-A or LICENSE-B" or "(LICENSE-A OR LICENSE-B)" to "LICENSE-A OR LICENSE-B" as per the Linux Kernel style document. Note that parenthesis are allowed so when they were used before we continue to use them. Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
480 lines
14 KiB
Text
480 lines
14 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
|
/*
|
|
* Copyright (C) 2016-2017 Intel Corporation
|
|
*
|
|
*<auto-generated>
|
|
* This code was generated by a tool based on
|
|
* handoffs from both Qsys and Quartus.
|
|
*
|
|
* Changes to this file may be lost if
|
|
* the code is regenerated.
|
|
*</auto-generated>
|
|
*/
|
|
|
|
#include "socfpga_arria10.dtsi"
|
|
|
|
/ {
|
|
model = "Altera SOCFPGA Arria 10";
|
|
compatible = "altr,socfpga-arria10", "altr,socfpga";
|
|
|
|
chosen {
|
|
/* Bootloader setting: uboot.rbf_filename */
|
|
cff-file = "ghrd_10as066n2.periph.rbf";
|
|
early-release-fpga-config;
|
|
};
|
|
|
|
soc {
|
|
u-boot,dm-pre-reloc;
|
|
clkmgr@ffd04000 {
|
|
u-boot,dm-pre-reloc;
|
|
clocks {
|
|
u-boot,dm-pre-reloc;
|
|
osc1 {
|
|
u-boot,dm-pre-reloc;
|
|
clock-frequency = <25000000>;
|
|
clock-output-names = "altera_arria10_hps_eosc1-clk";
|
|
};
|
|
|
|
cb_intosc_ls_clk {
|
|
u-boot,dm-pre-reloc;
|
|
clock-frequency = <60000000>;
|
|
clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
|
|
};
|
|
|
|
f2s_free_clk {
|
|
u-boot,dm-pre-reloc;
|
|
clock-frequency = <200000000>;
|
|
clock-output-names = "altera_arria10_hps_f2h_free-clk";
|
|
};
|
|
|
|
main_pll {
|
|
u-boot,dm-pre-reloc;
|
|
/*
|
|
* Address Block: soc_clock_manager_OCP_SLV.
|
|
* i_clk_mgr_mainpllgrp
|
|
*/
|
|
altr,of_reg_value = <
|
|
0 /* Field: vco0.psrc */
|
|
1 /* Field: vco1.denom */
|
|
191 /* Field: vco1.numer */
|
|
0 /* Field: mpuclk */
|
|
0 /* Field: mpuclk.cnt */
|
|
0 /* Field: mpuclk.src */
|
|
0 /* Field: nocclk */
|
|
0 /* Field: nocclk.cnt */
|
|
0 /* Field: nocclk.src */
|
|
900 /* Field: cntr2clk.cnt */
|
|
900 /* Field: cntr3clk.cnt */
|
|
900 /* Field: cntr4clk.cnt */
|
|
900 /* Field: cntr5clk.cnt */
|
|
900 /* Field: cntr6clk.cnt */
|
|
900 /* Field: cntr7clk.cnt */
|
|
0 /* Field: cntr7clk.src */
|
|
900 /* Field: cntr8clk.cnt */
|
|
900 /* Field: cntr9clk.cnt */
|
|
0 /* Field: cntr9clk.src */
|
|
900 /* Field: cntr15clk.cnt */
|
|
0 /* Field: nocdiv.l4mainclk */
|
|
0 /* Field: nocdiv.l4mpclk */
|
|
2 /* Field: nocdiv.l4spclk */
|
|
0 /* Field: nocdiv.csatclk */
|
|
1 /* Field: nocdiv.cstraceclk */
|
|
1 /* Field: nocdiv.cspdbgclk */
|
|
>;
|
|
};
|
|
|
|
periph_pll {
|
|
u-boot,dm-pre-reloc;
|
|
/*
|
|
* Address Block: soc_clock_manager_OCP_SLV.
|
|
* i_clk_mgr_perpllgrp
|
|
*/
|
|
altr,of_reg_value = <
|
|
0 /* Field: vco0.psrc */
|
|
1 /* Field: vco1.denom */
|
|
159 /* Field: vco1.numer */
|
|
7 /* Field: cntr2clk.cnt */
|
|
1 /* Field: cntr2clk.src */
|
|
900 /* Field: cntr3clk.cnt */
|
|
1 /* Field: cntr3clk.src */
|
|
19 /* Field: cntr4clk.cnt */
|
|
1 /* Field: cntr4clk.src */
|
|
499 /* Field: cntr5clk.cnt */
|
|
1 /* Field: cntr5clk.src */
|
|
9 /* Field: cntr6clk.cnt */
|
|
1 /* Field: cntr6clk.src */
|
|
900 /* Field: cntr7clk.cnt */
|
|
900 /* Field: cntr8clk.cnt */
|
|
0 /* Field: cntr8clk.src */
|
|
900 /* Field: cntr9clk.cnt */
|
|
0 /* Field: emacctl.emac0sel */
|
|
0 /* Field: emacctl.emac1sel */
|
|
0 /* Field: emacctl.emac2sel */
|
|
32000 /* Field: gpiodiv.gpiodbclk */
|
|
>;
|
|
};
|
|
|
|
altera {
|
|
u-boot,dm-pre-reloc;
|
|
/*
|
|
* Address Block: soc_clock_manager_OCP_SLV.
|
|
* i_clk_mgr_alteragrp
|
|
*/
|
|
altr,of_reg_value = <
|
|
0x0384000b /* Register: nocclk */
|
|
0x03840001 /* Register: mpuclk */
|
|
>;
|
|
};
|
|
};
|
|
};
|
|
|
|
/*
|
|
* Driver: altera_arria10_soc_3v_io48_pin_mux_arria10_uboot_driver
|
|
* Binding: pinmux
|
|
*/
|
|
i_io48_pin_mux: pinmux@0xffd07000 {
|
|
u-boot,dm-pre-reloc;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "pinctrl-single";
|
|
reg = <0xffd07000 0x00000800>;
|
|
reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
|
|
|
|
/*
|
|
* Address Block: soc_3v_io48_pin_mux_OCP_SLV.
|
|
* i_io48_pin_mux_shared_3v_io_grp
|
|
*/
|
|
shared {
|
|
u-boot,dm-pre-reloc;
|
|
reg = <0xffd07000 0x00000200>;
|
|
pinctrl-single,register-width = <32>;
|
|
pinctrl-single,function-mask = <0x0000000f>;
|
|
pinctrl-single,pins =
|
|
/* Reg: pinmux_shared_io_q1_1 */
|
|
<0x00000000 0x00000008>,
|
|
/* Reg: pinmux_shared_io_q1_2 */
|
|
<0x00000004 0x00000008>,
|
|
/* Reg: pinmux_shared_io_q1_3 */
|
|
<0x00000008 0x00000008>,
|
|
/* Reg: pinmux_shared_io_q1_4 */
|
|
<0x0000000c 0x00000008>,
|
|
/* Reg: pinmux_shared_io_q1_5 */
|
|
<0x00000010 0x00000008>,
|
|
/* Reg: pinmux_shared_io_q1_6 */
|
|
<0x00000014 0x00000008>,
|
|
/* Reg: pinmux_shared_io_q1_7 */
|
|
<0x00000018 0x00000008>,
|
|
/* Reg: pinmux_shared_io_q1_8 */
|
|
<0x0000001c 0x00000008>,
|
|
/* Reg: pinmux_shared_io_q1_9 */
|
|
<0x00000020 0x00000008>,
|
|
/* Reg: pinmux_shared_io_q1_10 */
|
|
<0x00000024 0x00000008>,
|
|
/* Reg: pinmux_shared_io_q1_11 */
|
|
<0x00000028 0x00000008>,
|
|
/* Reg: pinmux_shared_io_q1_12 */
|
|
<0x0000002c 0x00000008>,
|
|
/* Reg: pinmux_shared_io_q2_1 */
|
|
<0x00000030 0x00000004>,
|
|
/* Reg: pinmux_shared_io_q2_2 */
|
|
<0x00000034 0x00000004>,
|
|
/* Reg: pinmux_shared_io_q2_3 */
|
|
<0x00000038 0x00000004>,
|
|
/* Reg: pinmux_shared_io_q2_4 */
|
|
<0x0000003c 0x00000004>,
|
|
/* Reg: pinmux_shared_io_q2_5 */
|
|
<0x00000040 0x00000004>,
|
|
/* Reg: pinmux_shared_io_q2_6 */
|
|
<0x00000044 0x00000004>,
|
|
/* Reg: pinmux_shared_io_q2_7 */
|
|
<0x00000048 0x00000004>,
|
|
/* Reg: pinmux_shared_io_q2_8 */
|
|
<0x0000004c 0x00000004>,
|
|
/* Reg: pinmux_shared_io_q2_9 */
|
|
<0x00000050 0x00000004>,
|
|
/* Reg: pinmux_shared_io_q2_10 */
|
|
<0x00000054 0x00000004>,
|
|
/* Reg: pinmux_shared_io_q2_11 */
|
|
<0x00000058 0x00000004>,
|
|
/* Reg: pinmux_shared_io_q2_12 */
|
|
<0x0000005c 0x00000004>,
|
|
/* Reg: pinmux_shared_io_q3_1 */
|
|
<0x00000060 0x00000003>,
|
|
/* Reg: pinmux_shared_io_q3_2 */
|
|
<0x00000064 0x00000003>,
|
|
/* Reg: pinmux_shared_io_q3_3 */
|
|
<0x00000068 0x00000003>,
|
|
/* Reg: pinmux_shared_io_q3_4 */
|
|
<0x0000006c 0x00000003>,
|
|
/* Reg: pinmux_shared_io_q3_5 */
|
|
<0x00000070 0x00000003>,
|
|
/* Reg: pinmux_shared_io_q3_6 */
|
|
<0x00000074 0x0000000f>,
|
|
/* Reg: pinmux_shared_io_q3_7 */
|
|
<0x00000078 0x0000000a>,
|
|
/* Reg: pinmux_shared_io_q3_8 */
|
|
<0x0000007c 0x0000000a>,
|
|
/* Reg: pinmux_shared_io_q3_9 */
|
|
<0x00000080 0x0000000a>,
|
|
/* Reg: pinmux_shared_io_q3_10 */
|
|
<0x00000084 0x0000000a>,
|
|
/* Reg: pinmux_shared_io_q3_11 */
|
|
<0x00000088 0x00000001>,
|
|
/* Reg: pinmux_shared_io_q3_12 */
|
|
<0x0000008c 0x00000001>,
|
|
/* Reg: pinmux_shared_io_q4_1 */
|
|
<0x00000090 0x00000000>,
|
|
/* Reg: pinmux_shared_io_q4_2 */
|
|
<0x00000094 0x00000000>,
|
|
/* Reg: pinmux_shared_io_q4_3 */
|
|
<0x00000098 0x0000000f>,
|
|
/* Reg: pinmux_shared_io_q4_4 */
|
|
<0x0000009c 0x0000000c>,
|
|
/* Reg: pinmux_shared_io_q4_5 */
|
|
<0x000000a0 0x0000000f>,
|
|
/* Reg: pinmux_shared_io_q4_6 */
|
|
<0x000000a4 0x0000000f>,
|
|
/* Reg: pinmux_shared_io_q4_7 */
|
|
<0x000000a8 0x0000000a>,
|
|
/* Reg: pinmux_shared_io_q4_8 */
|
|
<0x000000ac 0x0000000a>,
|
|
/* Reg: pinmux_shared_io_q4_9 */
|
|
<0x000000b0 0x0000000c>,
|
|
/* Reg: pinmux_shared_io_q4_10 */
|
|
<0x000000b4 0x0000000c>,
|
|
/* Reg: pinmux_shared_io_q4_11 */
|
|
<0x000000b8 0x0000000c>,
|
|
/* Reg: pinmux_shared_io_q4_12 */
|
|
<0x000000bc 0x0000000c>;
|
|
};
|
|
|
|
/*
|
|
* Address Block: soc_3v_io48_pin_mux_OCP_SLV.
|
|
* i_io48_pin_mux_dedicated_io_grp
|
|
*/
|
|
dedicated {
|
|
u-boot,dm-pre-reloc;
|
|
reg = <0xffd07200 0x00000200>;
|
|
pinctrl-single,register-width = <32>;
|
|
pinctrl-single,function-mask = <0x0000000f>;
|
|
pinctrl-single,pins =
|
|
/* Reg: pinmux_dedicated_io_4 */
|
|
<0x0000000c 0x00000008>,
|
|
/* Reg: pinmux_dedicated_io_5 */
|
|
<0x00000010 0x00000008>,
|
|
/* Reg: pinmux_dedicated_io_6 */
|
|
<0x00000014 0x00000008>,
|
|
/* Regi: pinmux_dedicated_io_7 */
|
|
<0x00000018 0x00000008>,
|
|
/* Reg: pinmux_dedicated_io_8 */
|
|
<0x0000001c 0x00000008>,
|
|
/* Reg: pinmux_dedicated_io_9 */
|
|
<0x00000020 0x00000008>,
|
|
/* Reg: pinmux_dedicated_io_10 */
|
|
<0x00000024 0x0000000a>,
|
|
/* Reg: pinmux_dedicated_io_11 */
|
|
<0x00000028 0x0000000a>,
|
|
/* Reg: pinmux_dedicated_io_12 */
|
|
<0x0000002c 0x00000008>,
|
|
/* Reg: pinmux_dedicated_io_13 */
|
|
<0x00000030 0x00000008>,
|
|
/* Reg: pinmux_dedicated_io_14 */
|
|
<0x00000034 0x00000008>,
|
|
/* Reg: pinmux_dedicated_io_15 */
|
|
<0x00000038 0x00000008>,
|
|
/* Reg: pinmux_dedicated_io_16 */
|
|
<0x0000003c 0x0000000d>,
|
|
/* Reg: pinmux_dedicated_io_17 */
|
|
<0x00000040 0x0000000d>;
|
|
};
|
|
|
|
/*
|
|
* Address Block: soc_3v_io48_pin_mux_OCP_SLV.
|
|
* i_io48_pin_mux_dedicated_io_grp
|
|
*/
|
|
dedicated_cfg {
|
|
u-boot,dm-pre-reloc;
|
|
reg = <0xffd07200 0x00000200>;
|
|
pinctrl-single,register-width = <32>;
|
|
pinctrl-single,function-mask = <0x003f3f3f>;
|
|
pinctrl-single,pins =
|
|
/* Reg: cfg_dedicated_io_bank */
|
|
<0x00000100 0x00000101>,
|
|
/* Reg: cfg_dedicated_io_1 */
|
|
<0x00000104 0x000b080a>,
|
|
/* Reg: cfg_dedicated_io_2 */
|
|
<0x00000108 0x000b080a>,
|
|
/* Reg: cfg_dedicated_io_3 */
|
|
<0x0000010c 0x000b080a>,
|
|
/* Reg: cfg_dedicated_io_4 */
|
|
<0x00000110 0x000a282a>,
|
|
/* Reg: cfg_dedicated_io_5 */
|
|
<0x00000114 0x000a282a>,
|
|
/* Reg: cfg_dedicated_io_6 */
|
|
<0x00000118 0x0008282a>,
|
|
/* Reg: cfg_dedicated_io_7 */
|
|
<0x0000011c 0x000a282a>,
|
|
/* Reg: cfg_dedicated_io_8 */
|
|
<0x00000120 0x000a282a>,
|
|
/* Reg: cfg_dedicated_io_9 */
|
|
<0x00000124 0x000a282a>,
|
|
/* Reg: cfg_dedicated_io_10 */
|
|
<0x00000128 0x00090000>,
|
|
/* Reg: cfg_dedicated_io_11 */
|
|
<0x0000012c 0x00090000>,
|
|
/* Reg: cfg_dedicated_io_12 */
|
|
<0x00000130 0x000b282a>,
|
|
/* Reg: cfg_dedicated_io_13 */
|
|
<0x00000134 0x000b282a>,
|
|
/* Reg: cfg_dedicated_io_14 */
|
|
<0x00000138 0x000b282a>,
|
|
/* Reg: cfg_dedicated_io_15 */
|
|
<0x0000013c 0x000b282a>,
|
|
/* Reg: cfg_dedicated_io_16 */
|
|
<0x00000140 0x0008282a>,
|
|
/* Reg: cfg_dedicated_io_17 */
|
|
<0x00000144 0x000a282a>;
|
|
};
|
|
|
|
/*
|
|
* Address Block: soc_3v_io48_pin_mux_OCP_SLV.
|
|
* i_io48_pin_mux_fpga_interface_grp
|
|
*/
|
|
fpga {
|
|
u-boot,dm-pre-reloc;
|
|
reg = <0xffd07400 0x00000100>;
|
|
pinctrl-single,register-width = <32>;
|
|
pinctrl-single,function-mask = <0x00000001>;
|
|
pinctrl-single,pins =
|
|
/* Reg: pinmux_emac0_usefpga */
|
|
<0x00000000 0x00000000>,
|
|
/* Reg: pinmux_emac1_usefpga */
|
|
<0x00000004 0x00000000>,
|
|
/* Reg: pinmux_emac2_usefpga */
|
|
<0x00000008 0x00000000>,
|
|
/* Reg: pinmux_i2c0_usefpga */
|
|
<0x0000000c 0x00000000>,
|
|
/* Reg: pinmux_i2c1_usefpga */
|
|
<0x00000010 0x00000000>,
|
|
/* Reg: pinmux_i2c_emac0_usefpga */
|
|
<0x00000014 0x00000000>,
|
|
/* Reg: pinmux_i2c_emac1_usefpga */
|
|
<0x00000018 0x00000000>,
|
|
/* Reg: pinmux_i2c_emac2_usefpga */
|
|
<0x0000001c 0x00000000>,
|
|
/* Reg: pinmux_nand_usefpga */
|
|
<0x00000020 0x00000000>,
|
|
/* Reg: pinmux_qspi_usefpga */
|
|
<0x00000024 0x00000000>,
|
|
/* Reg: pinmux_sdmmc_usefpga */
|
|
<0x00000028 0x00000000>,
|
|
/* Reg: pinmux_spim0_usefpga */
|
|
<0x0000002c 0x00000000>,
|
|
/* Reg: pinmux_spim1_usefpga */
|
|
<0x00000030 0x00000000>,
|
|
/* Reg: pinmux_spis0_usefpga */
|
|
<0x00000034 0x00000000>,
|
|
/* Reg: pinmux_spis1_usefpga */
|
|
<0x00000038 0x00000000>,
|
|
/* Reg: pinmux_uart0_usefpga */
|
|
<0x0000003c 0x00000000>,
|
|
/* Reg: pinmux_uart1_usefpga */
|
|
<0x00000040 0x00000000>;
|
|
};
|
|
};
|
|
|
|
i_noc: noc@0xffd10000 {
|
|
u-boot,dm-pre-reloc;
|
|
compatible = "altr,socfpga-a10-noc";
|
|
reg = <0xffd10000 0x00008000>;
|
|
reg-names = "mpu_m0";
|
|
|
|
firewall {
|
|
u-boot,dm-pre-reloc;
|
|
/*
|
|
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
|
* I_NOC.mpu_m0.
|
|
* noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
|
|
* mpuregion0addr.base
|
|
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
|
* I_NOC.mpu_m0.
|
|
* noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
|
|
* mpuregion0addr.limit
|
|
*/
|
|
altr,mpu0 = <0x00000000 0x0000ffff>;
|
|
/*
|
|
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
|
* I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.
|
|
* hpsregion0addr.base
|
|
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
|
* I_NOC.mpu_m0.noc_fw_ddr_l3_ddr_scr.
|
|
* hpsregion0addr.limit
|
|
*/
|
|
altr,l3-0 = <0x00000000 0x0000ffff>;
|
|
/*
|
|
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
|
* I_NOC.mpu_m0.
|
|
* noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
|
|
* fpga2sdram0region0addr.base
|
|
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
|
* I_NOC.mpu_m0.
|
|
* noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
|
|
* fpga2sdram0region0addr.limit
|
|
*/
|
|
altr,fpga2sdram0-0 = <0x00000000 0x0000ffff>;
|
|
/*
|
|
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
|
* I_NOC.mpu_m0.
|
|
* noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
|
|
* fpga2sdram1region0addr.base
|
|
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
|
* I_NOC.mpu_m0.
|
|
* noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
|
|
* fpga2sdram1region0addr.limit
|
|
*/
|
|
altr,fpga2sdram1-0 = <0x00000000 0x0000ffff>;
|
|
/*
|
|
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
|
* I_NOC.mpu_m0.
|
|
* noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
|
|
* fpga2sdram2region0addr.base
|
|
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.
|
|
* I_NOC.mpu_m0.
|
|
* noc_fw_ddr_mpu_fpga2sdram_ddr_scr.
|
|
* fpga2sdram2region0addr.limit
|
|
*/
|
|
altr,fpga2sdram2-0 = <0x00000000 0x0000ffff>;
|
|
};
|
|
};
|
|
|
|
hps_fpgabridge0: fpgabridge@0 {
|
|
compatible = "altr,socfpga-hps2fpga-bridge";
|
|
altr,init-val = <1>;
|
|
};
|
|
|
|
hps_fpgabridge1: fpgabridge@1 {
|
|
compatible = "altr,socfpga-lwhps2fpga-bridge";
|
|
altr,init-val = <1>;
|
|
};
|
|
|
|
hps_fpgabridge2: fpgabridge@2 {
|
|
compatible = "altr,socfpga-fpga2hps-bridge";
|
|
altr,init-val = <1>;
|
|
};
|
|
|
|
hps_fpgabridge3: fpgabridge@3 {
|
|
compatible = "altr,socfpga-fpga2sdram0-bridge";
|
|
altr,init-val = <1>;
|
|
};
|
|
|
|
hps_fpgabridge4: fpgabridge@4 {
|
|
compatible = "altr,socfpga-fpga2sdram1-bridge";
|
|
altr,init-val = <0>;
|
|
};
|
|
|
|
hps_fpgabridge5: fpgabridge@5 {
|
|
compatible = "altr,socfpga-fpga2sdram2-bridge";
|
|
altr,init-val = <1>;
|
|
};
|
|
};
|
|
};
|