mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 09:48:16 +00:00
0e60aa85c8
Signed-off-by: Dirk Eibach <eibach@gdsys.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
251 lines
11 KiB
C
251 lines
11 KiB
C
#include <common.h>
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#include <asm/ppc4xx.h>
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#include <asm/ppc405.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <gdsys_fpga.h>
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#include "405ex.h"
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#define REFLECTION_TESTPATTERN 0xdede
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#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
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DECLARE_GLOBAL_DATA_PTR;
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int get_fpga_state(unsigned dev)
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{
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return gd->fpga_state[dev];
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}
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void print_fpga_state(unsigned dev)
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{
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if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED)
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puts(" Waiting for FPGA-DONE timed out.\n");
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if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
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puts(" FPGA reflection test failed.\n");
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}
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int board_early_init_f(void)
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{
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u32 val;
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/*--------------------------------------------------------------------+
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| Interrupt controller setup
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+--------------------------------------------------------------------+
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+---------------------------------------------------------------------+
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|Interrupt| Source | Pol. | Sensi.| Crit. |
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+---------+-----------------------------------+-------+-------+-------+
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| IRQ 00 | UART0 | High | Level | Non |
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| IRQ 01 | UART1 | High | Level | Non |
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| IRQ 02 | IIC0 | High | Level | Non |
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| IRQ 03 | TBD | High | Level | Non |
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| IRQ 04 | TBD | High | Level | Non |
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| IRQ 05 | EBM | High | Level | Non |
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| IRQ 06 | BGI | High | Level | Non |
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| IRQ 07 | IIC1 | Rising| Edge | Non |
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| IRQ 08 | SPI | High | Lvl/ed| Non |
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| IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non |
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| IRQ 10 | MAL TX EOB | High | Level | Non |
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| IRQ 11 | MAL RX EOB | High | Level | Non |
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| IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non |
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| IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non |
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| IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non |
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| IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non |
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| IRQ 16 | PCIE0 AL | high | Level | Non |
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| IRQ 17 | PCIE0 VPD access | rising| Edge | Non |
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| IRQ 18 | PCIE0 hot reset request | rising| Edge | Non |
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| IRQ 19 | PCIE0 hot reset request | faling| Edge | Non |
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| IRQ 20 | PCIE0 TCR | High | Level | Non |
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| IRQ 21 | PCIE0 MSI level0 | High | Level | Non |
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| IRQ 22 | PCIE0 MSI level1 | High | Level | Non |
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| IRQ 23 | Security EIP-94 | High | Level | Non |
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| IRQ 24 | EMAC0 interrupt | High | Level | Non |
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| IRQ 25 | EMAC1 interrupt | High | Level | Non |
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| IRQ 26 | PCIE0 MSI level2 | High | Level | Non |
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| IRQ 27 | External IRQ 4 | pgm H | Pgm | Non |
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| IRQ 28 | UIC2 Non-critical Int. | High | Level | Non |
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| IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. |
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| IRQ 30 | UIC1 Non-critical Int. | High | Level | Non |
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| IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. |
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|----------------------------------------------------------------------
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| IRQ 32 | MAL Serr | High | Level | Non |
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| IRQ 33 | MAL Txde | High | Level | Non |
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| IRQ 34 | MAL Rxde | High | Level | Non |
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| IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non |
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| IRQ 36 | PCIE0 DCR Error | High | Level | Non |
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| IRQ 37 | EBC | High |Lvl Edg| Non |
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| IRQ 38 | NDFC | High | Level | Non |
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| IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non |
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| IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non |
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| IRQ 41 | PCIE1 AL | high | Level | Non |
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| IRQ 42 | PCIE1 VPD access | rising| edge | Non |
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| IRQ 43 | PCIE1 hot reset request | rising| Edge | Non |
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| IRQ 44 | PCIE1 hot reset request | faling| Edge | Non |
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| IRQ 45 | PCIE1 TCR | High | Level | Non |
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| IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non |
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| IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
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| IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
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| IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non |
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| IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non |
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| IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
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| IRQ 52 | GPT Compare Timer 5 | high | Edge | Non |
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| IRQ 53 | GPT Compare Timer 6 | high | Edge | Non |
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| IRQ 54 | GPT Compare Timer 7 | high | Edge | Non |
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| IRQ 55 | Serial ROM | High | Level | Non |
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| IRQ 56 | GPT Decrement Pulse | High | Level | Non |
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| IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non |
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| IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non |
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| IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non |
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| IRQ 60 | EMAC0 Wake-up | High | Level | Non |
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| IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non |
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| IRQ 62 | EMAC1 Wake-up | High | Level | Non |
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|----------------------------------------------------------------------
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| IRQ 64 | PE0 AL | High | Level | Non |
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| IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
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| IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
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| IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
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| IRQ 68 | PE0 TCR | High | Level | Non |
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| IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
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| IRQ 70 | PE0 DCR Error | High | Level | Non |
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| IRQ 71 | Reserved | N/A | N/A | Non |
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| IRQ 72 | PE1 AL | High | Level | Non |
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| IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
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| IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
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| IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
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| IRQ 76 | PE1 TCR | High | Level | Non |
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| IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
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| IRQ 78 | PE1 DCR Error | High | Level | Non |
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| IRQ 79 | Reserved | N/A | N/A | Non |
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| IRQ 80 | PE2 AL | High | Level | Non |
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| IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
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| IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
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| IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
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| IRQ 84 | PE2 TCR | High | Level | Non |
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| IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
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| IRQ 86 | PE2 DCR Error | High | Level | Non |
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| IRQ 87 | Reserved | N/A | N/A | Non |
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| IRQ 88 | External IRQ(5) | Progr | Progr | Non |
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| IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
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| IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
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| IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
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| IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
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| IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
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| IRQ 94 | Reserved | N/A | N/A | Non |
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| IRQ 95 | Reserved | N/A | N/A | Non |
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|---------------------------------------------------------------------
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+---------+-----------------------------------+-------+-------+------*/
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/*--------------------------------------------------------------------+
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| Initialise UIC registers. Clear all interrupts. Disable all
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| interrupts.
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| Set critical interrupt values. Set interrupt polarities. Set
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| interrupt trigger levels. Make bit 0 High priority. Clear all
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| interrupts again.
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+-------------------------------------------------------------------*/
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mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */
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mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */
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mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */
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mtdcr(UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */
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mtdcr(UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
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mtdcr(UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
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mtdcr(UIC2SR, 0x00000000); /* clear all interrupts */
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mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */
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mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */
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mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */
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mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */
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mtdcr(UIC1PR, 0xfffac785); /* Set Interrupt Polarities */
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mtdcr(UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */
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mtdcr(UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
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mtdcr(UIC1SR, 0x00000000); /* clear all interrupts */
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mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */
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mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */
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mtdcr(UIC0ER, 0x0000000a); /* Disable all interrupts */
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/* Except cascade UIC0 and UIC1 */
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mtdcr(UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */
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mtdcr(UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */
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mtdcr(UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */
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mtdcr(UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
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mtdcr(UIC0SR, 0x00000000); /* clear all interrupts */
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mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */
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/*
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* Note: Some cores are still in reset when the chip starts, so
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* take them out of reset
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*/
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mtsdr(SDR0_SRST, 0);
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/*
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* Configure PFC (Pin Function Control) registers
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*/
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val = SDR0_PFC1_GPT_FREQ;
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mtsdr(SDR0_PFC1, val);
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return 0;
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}
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int board_early_init_r(void)
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{
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unsigned k;
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unsigned ctr;
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for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
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gd->fpga_state[k] = 0;
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/*
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* reset FPGA
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*/
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gd405ex_init();
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gd405ex_set_fpga_reset(1);
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gd405ex_setup_hw();
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for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
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ctr = 0;
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while (!gd405ex_get_fpga_done(k)) {
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udelay(100000);
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if (ctr++ > 5) {
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gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
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break;
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}
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}
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}
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udelay(10);
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gd405ex_set_fpga_reset(0);
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for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
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struct ihs_fpga *fpga =
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(struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k);
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#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
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u16 *reflection_target = &fpga->reflection_low;
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#else
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u16 *reflection_target = &fpga->reflection_high;
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#endif
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/*
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* wait for fpga out of reset
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*/
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ctr = 0;
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while (1) {
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out_le16(&fpga->reflection_low,
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REFLECTION_TESTPATTERN);
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if (in_le16(reflection_target) ==
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REFLECTION_TESTPATTERN_INV)
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break;
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udelay(100000);
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if (ctr++ > 5) {
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gd->fpga_state[k] |=
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FPGA_STATE_REFLECTION_FAILED;
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break;
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}
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}
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}
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return 0;
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}
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