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https://github.com/AsahiLinux/u-boot
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b8ce78a8c9
As imx28 family of SoCs is NOT supporting the Common Clock Framework (CCF) the 'clks' property shall NOT be enabled by default. Without this change u-boot proper before relocation tries to bind driver (which doesn't exists) for this device. As a result, pre-relocation DTB parsing is finished with error and the board hangs in a very early stage of u-boot proper boot process. Signed-off-by: Lukasz Majewski <lukma@denx.de>
93 lines
1.5 KiB
Text
93 lines
1.5 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*
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* SPDX-License-Identifier: GPL-2.0+ or X11
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*/
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/*
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* The minimal augmentation DTS U-Boot file to allow eMMC driver
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* configuration in SPL for falcon boot.
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*/
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#include "imx28-u-boot.dtsi"
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/ {
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aliases {
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/delete-property/ spi1;
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/delete-property/ usbphy0;
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/delete-property/ usbphy1;
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};
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apb@80000000 {
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bootph-pre-ram;
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apbh@80000000 {
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bootph-pre-ram;
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};
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apbx@80040000 {
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bootph-pre-ram;
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};
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};
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};
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&clks {
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bootph-pre-ram;
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status = "disable";
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};
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&duart {
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/delete-property/ clocks;
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bootph-pre-ram;
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type = <1>; /* TYPE_PL011 */
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};
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&gpio0 {
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bootph-pre-ram;
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};
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&mac0 {
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phy-mode = "rmii";
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pinctrl-names = "default";
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pinctrl-0 = <&mac0_pins_a>;
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phy-supply = <®_fec_3v3>;
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phy-reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <1>;
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phy-reset-post-delay = <1>;
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status = "okay";
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fixed-link {
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speed = <100>;
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full-duplex;
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};
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};
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&pinctrl {
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/delete-property/ pinctrl-names;
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/delete-property/ pinctrl-0;
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bootph-pre-ram;
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};
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®_fec_3v3 {
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gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-boot-on;
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};
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&ssp0 {
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bootph-pre-ram;
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};
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&ssp3 {
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num-cs = <2>;
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spi-max-frequency = <40000000>;
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bootph-pre-ram;
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};
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/delete-node/ &ssp2;
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/delete-node/ &usb0;
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/delete-node/ &usbphy0;
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/delete-node/ &usb1;
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/delete-node/ &usbphy1;
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/delete-node/ &hog_pins_a;
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/delete-node/ &hog_pins_tiva;
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/delete-node/ &hog_pins_coding;
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