mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 17:07:38 +00:00
5a2416fd99
Tag the serial nodes with bootph-all in order to have these nodes and the drivers available before relocation. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
396 lines
10 KiB
Text
396 lines
10 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP ls2080a SOC common device tree source
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*
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* Copyright 2020-2021 NXP
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* Copyright 2013-2015 Freescale Semiconductor, Inc.
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*/
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#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
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/ {
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compatible = "fsl,ls2080a";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &serial0;
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serial1 = &serial1;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0 0x80000000>;
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/* DRAM space - 1, size : 2 GB DRAM */
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};
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sysclk: sysclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "sysclk";
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};
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gic: interrupt-controller@6000000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
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<0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <1 9 0x4>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
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<1 14 0x8>, /* Physical Non-Secure PPI, active-low */
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<1 11 0x8>, /* Virtual PPI, active-low */
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<1 10 0x8>; /* Hypervisor PPI, active-low */
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
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clockgen: clocking@1300000 {
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compatible = "fsl,ls2080a-clockgen";
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reg = <0 0x1300000 0 0xa0000>;
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#clock-cells = <2>;
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clocks = <&sysclk>;
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};
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serial0: serial@21c0500 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21c0500 0x0 0x100>;
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(4)>;
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interrupts = <0 32 0x4>; /* Level high type */
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bootph-all;
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};
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serial1: serial@21c0600 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21c0600 0x0 0x100>;
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(4)>;
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interrupts = <0 32 0x4>; /* Level high type */
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bootph-all;
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};
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};
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i2c0: i2c@2000000 {
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status = "disabled";
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2000000 0x0 0x10000>;
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interrupts = <0 34 0x4>; /* Level high type */
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};
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i2c1: i2c@2010000 {
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status = "disabled";
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2010000 0x0 0x10000>;
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interrupts = <0 34 0x4>; /* Level high type */
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};
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i2c2: i2c@2020000 {
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status = "disabled";
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2020000 0x0 0x10000>;
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interrupts = <0 35 0x4>; /* Level high type */
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};
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i2c3: i2c@2030000 {
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status = "disabled";
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2030000 0x0 0x10000>;
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interrupts = <0 35 0x4>; /* Level high type */
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};
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dspi: dspi@2100000 {
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compatible = "fsl,vf610-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2100000 0x0 0x10000>;
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interrupts = <0 26 0x4>; /* Level high type */
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spi-num-chipselects = <6>;
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};
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qspi: quadspi@1550000 {
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compatible = "fsl,ls2080a-qspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x20c0000 0x0 0x10000>,
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<0x0 0x20000000 0x0 0x10000000>;
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reg-names = "QuadSPI", "QuadSPI-memory";
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status = "disabled";
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};
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esdhc: esdhc@0 {
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compatible = "fsl,esdhc";
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reg = <0x0 0x2140000 0x0 0x10000>;
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interrupts = <0 28 0x4>; /* Level high type */
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little-endian;
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bus-width = <4>;
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};
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gpio0: gpio@2300000 {
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compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
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reg = <0x0 0x2300000 0x0 0x10000>;
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interrupts = <0 36 0x4>; /* Level high type */
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gpio-controller;
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little-endian;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio@2310000 {
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compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
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reg = <0x0 0x2310000 0x0 0x10000>;
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interrupts = <0 36 0x4>; /* Level high type */
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gpio-controller;
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little-endian;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@2320000 {
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compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
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reg = <0x0 0x2320000 0x0 0x10000>;
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interrupts = <0 37 0x4>; /* Level high type */
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gpio-controller;
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little-endian;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@2330000 {
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compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
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reg = <0x0 0x2330000 0x0 0x10000>;
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interrupts = <0 37 0x4>; /* Level high type */
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gpio-controller;
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little-endian;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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usb0: usb3@3100000 {
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compatible = "fsl,layerscape-dwc3";
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reg = <0x0 0x3100000 0x0 0x10000>;
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interrupts = <0 80 0x4>; /* Level high type */
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dr_mode = "host";
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};
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usb1: usb3@3110000 {
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compatible = "fsl,layerscape-dwc3";
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reg = <0x0 0x3110000 0x0 0x10000>;
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interrupts = <0 81 0x4>; /* Level high type */
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dr_mode = "host";
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};
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pcie1: pcie@3400000 {
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compatible = "fsl,ls-pcie", "snps,dw-pcie";
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reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
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0x00 0x03480000 0x0 0x80000 /* lut registers */
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0x10 0x00000000 0x0 0x20000>; /* configuration space */
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reg-names = "dbi", "lut", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <4>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x10 0x00020000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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pcie2: pcie@3500000 {
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compatible = "fsl,ls-pcie", "snps,dw-pcie";
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reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
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0x00 0x03580000 0x0 0x80000 /* lut registers */
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0x12 0x00000000 0x0 0x20000>; /* configuration space */
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reg-names = "dbi", "lut", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <4>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x12 0x00020000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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pcie3: pcie@3600000 {
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compatible = "fsl,ls-pcie", "snps,dw-pcie";
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reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
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0x00 0x03680000 0x0 0x80000 /* lut registers */
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0x14 0x00000000 0x0 0x20000>; /* configuration space */
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reg-names = "dbi", "lut", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <8>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x14 0x00020000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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pcie4: pcie@3700000 {
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compatible = "fsl,ls-pcie", "snps,dw-pcie";
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reg = <0x00 0x03700000 0x0 0x80000 /* dbi registers */
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0x00 0x03780000 0x0 0x80000 /* lut registers */
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0x16 0x00000000 0x0 0x20000>; /* configuration space */
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reg-names = "dbi", "lut", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <4>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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sata: sata@3200000 {
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compatible = "fsl,ls2080a-ahci";
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reg = <0x0 0x3200000 0x0 0x10000>;
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interrupts = <0 133 0x4>; /* Level high type */
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status = "disabled";
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};
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crypto: crypto@8000000 {
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compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
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fsl,sec-era = <8>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x00 0x8000000 0x100000>;
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reg = <0x00 0x8000000 0x0 0x100000>;
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interrupts = <0 139 0x4>; /* Level high type */
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dma-coherent;
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sec_jr0: jr@10000 {
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compatible = "fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x10000 0x10000>;
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interrupts = <0 140 0x4>; /* Level high type */
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};
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sec_jr1: jr@20000 {
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compatible = "fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x20000 0x10000>;
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interrupts = <0 141 0x4>; /* Level high type */
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};
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sec_jr2: jr@30000 {
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compatible = "fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x30000 0x10000>;
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interrupts = <0 142 0x4>; /* Level high type */
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};
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sec_jr3: jr@40000 {
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compatible = "fsl,sec-v5.0-job-ring",
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"fsl,sec-v4.0-job-ring";
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reg = <0x40000 0x10000>;
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interrupts = <0 143 0x4>; /* Level high type */
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};
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};
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fsl_mc: fsl-mc@80c000000 {
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compatible = "fsl,qoriq-mc", "simple-mfd";
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reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
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<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
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#address-cells = <3>;
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#size-cells = <1>;
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/*
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* Region type 0x0 - MC portals
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* Region type 0x1 - QBMAN portals
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*/
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ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
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0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
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dpmacs {
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compatible = "simple-mfd";
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#address-cells = <1>;
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#size-cells = <0>;
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dpmac1: dpmac@1 {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0x1>;
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status = "disabled";
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};
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dpmac2: dpmac@2 {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0x2>;
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status = "disabled";
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};
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dpmac3: dpmac@3 {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0x3>;
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status = "disabled";
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};
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dpmac4: dpmac@4 {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0x4>;
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status = "disabled";
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};
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dpmac5: dpmac@5 {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0x5>;
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status = "disabled";
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};
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dpmac6: dpmac@6 {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0x6>;
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status = "disabled";
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};
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dpmac7: dpmac@7 {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0x7>;
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status = "disabled";
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};
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dpmac8: dpmac@8 {
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compatible = "fsl,qoriq-mc-dpmac";
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reg = <0x8>;
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status = "disabled";
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};
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};
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};
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emdio1: mdio@8B96000 {
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compatible = "fsl,ls-mdio";
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reg = <0x0 0x8B96000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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emdio2: mdio@8B97000 {
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compatible = "fsl,ls-mdio";
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reg = <0x0 0x8B97000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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