mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 15:41:40 +00:00
442a69c143
The commit b583348ca8 ("image: fit: Align hash output buffers") places
the hash output buffer at the .bss section. However, AST2600 by default
executes SPL in the NOR flash XIP way. This results in the hash output
cannot be written to the buffer as it is located at the R/X only region.
We need to move the .bss section out of the SPL body to the DRAM space,
where hash output can be written to. This patch includes:
- Define the .bss section base and size
- A new SPL linker script is added with a separate .bss region specified
- Enable CONFIG_SPL_SEPARATE_BSS kconfig option
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Neal Liu <neal_liu@aspeedtech.com>
92 lines
2.2 KiB
Text
92 lines
2.2 KiB
Text
CONFIG_ARM=y
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CONFIG_SYS_DCACHE_OFF=y
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CONFIG_SPL_SYS_THUMB_BUILD=y
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CONFIG_SPL_LDSCRIPT="arch/arm/mach-aspeed/ast2600/u-boot-spl.lds"
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CONFIG_ARCH_ASPEED=y
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CONFIG_SYS_TEXT_BASE=0x80000000
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CONFIG_SYS_MALLOC_LEN=0x2000000
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CONFIG_SYS_MALLOC_F_LEN=0x800
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CONFIG_ASPEED_AST2600=y
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CONFIG_TARGET_EVB_AST2600=y
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_ENV_SIZE=0x10000
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CONFIG_DM_GPIO=y
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CONFIG_DEFAULT_DEVICE_TREE="ast2600-evb"
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CONFIG_SPL_SERIAL=y
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CONFIG_SPL_STACK_R_ADDR=0x83000000
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CONFIG_SPL_SIZE_LIMIT=0x10000
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CONFIG_SPL=y
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# CONFIG_ARMV7_NONSEC is not set
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CONFIG_SYS_LOAD_ADDR=0x83000000
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# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
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CONFIG_FIT=y
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CONFIG_SPL_FIT_SIGNATURE=y
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CONFIG_SPL_LOAD_FIT=y
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CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000
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# CONFIG_USE_SPL_FIT_GENERATOR is not set
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="console=ttyS4,115200n8 root=/dev/ram rw"
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CONFIG_USE_BOOTCOMMAND=y
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CONFIG_BOOTCOMMAND="run bootspi"
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# CONFIG_DISPLAY_CPUINFO is not set
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CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
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CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
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CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
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CONFIG_SPL_BSS_START_ADDR=0x83000000
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CONFIG_SPL_BSS_MAX_SIZE=0x1000000
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CONFIG_SPL_SYS_MALLOC_SIMPLE=y
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000000
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CONFIG_SPL_SEPARATE_BSS=y
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CONFIG_SPL_FIT_IMAGE_TINY=y
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CONFIG_SPL_DM_RESET=y
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CONFIG_SPL_RAM_SUPPORT=y
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CONFIG_SPL_RAM_DEVICE=y
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CONFIG_HUSH_PARSER=y
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CONFIG_SYS_CBSIZE=256
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CONFIG_SYS_PBSIZE=276
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_DHCP=y
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CONFIG_BOOTP_BOOTFILESIZE=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_ENV_OVERWRITE=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_SPL_DM=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_REGMAP=y
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CONFIG_SPL_OF_TRANSLATE=y
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CONFIG_CLK=y
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CONFIG_SPL_CLK=y
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CONFIG_DM_HASH=y
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CONFIG_HASH_ASPEED=y
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CONFIG_ASPEED_ACRY=y
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CONFIG_ASPEED_GPIO=y
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CONFIG_DM_I2C=y
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CONFIG_MISC=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ASPEED=y
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CONFIG_PHY_REALTEK=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_FTGMAC100=y
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CONFIG_ASPEED_MDIO=y
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CONFIG_PHY=y
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CONFIG_PINCTRL=y
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CONFIG_RAM=y
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CONFIG_SPL_RAM=y
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CONFIG_DM_RESET=y
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CONFIG_DM_SERIAL=y
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CONFIG_SYS_NS16550=y
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CONFIG_SYSRESET=y
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CONFIG_SPL_SYSRESET=y
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CONFIG_WDT=y
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CONFIG_SHA384=y
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CONFIG_HEXDUMP=y
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# CONFIG_EFI_LOADER is not set
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