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https://github.com/AsahiLinux/u-boot
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2f8a6db5d8
In order to finish moving this symbol to Kconfig for all platforms, we need to do a few more things. First, for all platforms that define this to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h. This entails also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk() and updating a few preprocessor tests. With that done, all platforms that define a value here can be converted to Kconfig, and a fall-back of zero is sufficiently safe to use (and what is used today in cases where code may or may not have this available). Make sure that code which calls this function includes <clock_legacy.h> to get the prototype. Signed-off-by: Tom Rini <trini@konsulko.com>
311 lines
7.9 KiB
C
311 lines
7.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2011 Andes Technology Corporation
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* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch-ag101/ag101.h>
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/*
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* CPU and Board Configuration Options
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*/
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#define CONFIG_USE_INTERRUPT
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#define CONFIG_BOOTP_SERVERIP
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_MEM_REMAP
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#endif
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#ifdef CONFIG_SKIP_LOWLEVEL_INIT
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#ifdef CONFIG_OF_CONTROL
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#undef CONFIG_OF_SEPARATE
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#endif
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#endif
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/*
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* Timer
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*/
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#define VERSION_CLOCK get_board_sys_clk()
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/*
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* Use Externel CLOCK or PCLK
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*/
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#undef CONFIG_FTRTC010_EXTCLK
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#ifndef CONFIG_FTRTC010_EXTCLK
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#define CONFIG_FTRTC010_PCLK
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#endif
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#ifdef CONFIG_FTRTC010_EXTCLK
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#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
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#else
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#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
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#endif
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#define TIMER_LOAD_VAL 0xffffffff
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/*
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* Real Time Clock
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*/
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#define CONFIG_RTC_FTRTC010
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/*
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* Real Time Clock Divider
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* RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
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*/
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#define OSC_5MHZ (5*1000000)
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#define OSC_CLK (4*OSC_5MHZ)
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#define RTC_DIV_COUNT (0.5) /* Why?? */
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/*
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* Serial console configuration
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*/
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/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
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#ifndef CONFIG_DM_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE -4
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#endif
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#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
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/*
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* Miscellaneous configurable options
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*/
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/*
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* AHB Controller configuration
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*/
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#define CONFIG_FTAHBC020S
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#ifdef CONFIG_FTAHBC020S
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#include <faraday/ftahbc020s.h>
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/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
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#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
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/*
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* CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
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* hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
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* in C language.
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*/
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#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
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(FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
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FTAHBC020S_SLAVE_BSR_SIZE(0xb))
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#endif
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/*
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* Watchdog
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*/
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#define CONFIG_FTWDT010_WATCHDOG
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/*
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* PMU Power controller configuration
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*/
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#define CONFIG_PMU
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#define CONFIG_FTPMU010_POWER
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#ifdef CONFIG_FTPMU010_POWER
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#include <faraday/ftpmu010.h>
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#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E
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#define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \
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FTPMU010_SDRAMHTC_EBIDATA_DCSR | \
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FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \
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FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
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FTPMU010_SDRAMHTC_CKE_DCSR | \
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FTPMU010_SDRAMHTC_DQM_DCSR | \
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FTPMU010_SDRAMHTC_SDCLK_DCSR)
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#endif
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/*
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* SDRAM controller configuration
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*/
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#define CONFIG_FTSDMC021
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#ifdef CONFIG_FTSDMC021
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#include <faraday/ftsdmc021.h>
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#define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \
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FTSDMC021_TP1_TRP(1) | \
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FTSDMC021_TP1_TRCD(1) | \
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FTSDMC021_TP1_TRF(3) | \
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FTSDMC021_TP1_TWR(1) | \
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FTSDMC021_TP1_TCL(2))
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#define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \
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FTSDMC021_TP2_INI_REFT(8) | \
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FTSDMC021_TP2_REF_INTV(0x180))
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/*
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* CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
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* hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
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* C language.
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*/
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#define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \
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FTSDMC021_CR1_DSZ(3) | \
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FTSDMC021_CR1_MBW(2) | \
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FTSDMC021_CR1_BNKSIZE(6))
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#define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \
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FTSDMC021_CR2_IREF | \
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FTSDMC021_CR2_ISMR)
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#define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
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#define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \
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CONFIG_SYS_FTSDMC021_BANK0_BASE)
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#define CONFIG_SYS_FTSDMC021_BANK1_BASE \
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(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
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#define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \
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CONFIG_SYS_FTSDMC021_BANK1_BASE)
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#endif
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/*
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* Physical Memory Map
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*/
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#ifdef CONFIG_SKIP_LOWLEVEL_INIT
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#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
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#else
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#ifdef CONFIG_MEM_REMAP
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#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
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#else
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#define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */
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#endif
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#endif
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#define PHYS_SDRAM_1 \
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(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
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#ifdef CONFIG_SKIP_LOWLEVEL_INIT
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#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
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#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
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#else
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#ifdef CONFIG_MEM_REMAP
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#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
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#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
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#else
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#define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */
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#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
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#endif
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#endif
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
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#ifdef CONFIG_MEM_REMAP
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
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GENERATED_GBL_DATA_SIZE)
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#else
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
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GENERATED_GBL_DATA_SIZE)
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#endif /* CONFIG_MEM_REMAP */
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/*
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* Static memory controller configuration
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*/
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#define CONFIG_FTSMC020
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#ifdef CONFIG_FTSMC020
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#include <faraday/ftsmc020.h>
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#define CONFIG_SYS_FTSMC020_CONFIGS { \
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{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
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{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
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}
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
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#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
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FTSMC020_BANK_SIZE_32M | \
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FTSMC020_BANK_MBW_32)
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#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
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FTSMC020_TPR_AST(1) | \
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FTSMC020_TPR_CTW(1) | \
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FTSMC020_TPR_ATI(1) | \
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FTSMC020_TPR_AT2(1) | \
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FTSMC020_TPR_WTC(1) | \
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FTSMC020_TPR_AHT(1) | \
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FTSMC020_TPR_TRNA(1))
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#endif
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/*
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* FLASH on ADP_AG101P is connected to BANK0
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* Just disalbe the other BANK to avoid detection error.
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*/
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#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
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FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
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FTSMC020_BANK_SIZE_32M | \
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FTSMC020_BANK_MBW_32)
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#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
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FTSMC020_TPR_CTW(3) | \
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FTSMC020_TPR_ATI(0xf) | \
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FTSMC020_TPR_AT2(3) | \
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FTSMC020_TPR_WTC(3) | \
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FTSMC020_TPR_AHT(3) | \
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FTSMC020_TPR_TRNA(0xf))
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#define FTSMC020_BANK1_CONFIG (0x00)
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#define FTSMC020_BANK1_TIMING (0x00)
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#endif /* CONFIG_FTSMC020 */
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/*
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* FLASH and environment organization
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*/
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/* use CFI framework */
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
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/* support JEDEC */
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/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
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#ifdef CONFIG_SKIP_LOWLEVEL_INIT
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#define PHYS_FLASH_1 0x80000000 /* BANK 0 */
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#else
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#ifdef CONFIG_MEM_REMAP
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#define PHYS_FLASH_1 0x80000000 /* BANK 0 */
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#else
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#define PHYS_FLASH_1 0x00000000 /* BANK 0 */
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#endif
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#endif /* CONFIG_MEM_REMAP */
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
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#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
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/* max number of memory banks */
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/*
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* There are 4 banks supported for this Controller,
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* but we have only 1 bank connected to flash on board
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*/
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#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#endif
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#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
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/* max number of sectors on one chip */
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#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
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#define CONFIG_SYS_MAX_FLASH_SECT 512
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/* environments */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 16 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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/* Initial Memory map for Linux*/
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#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
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/* Increase max gunzip size */
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#define CONFIG_SYS_BOOTM_LEN (64 << 20)
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#endif /* __CONFIG_H */
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