mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-17 08:43:07 +00:00
8c59f2023c
U-Boot SPL on the generic RISC-V CPU supports two boot flows, directly jumping to the image and via OpenSBI firmware. In the first case, both U-Boot SPL and proper must be compiled to run in the same privilege mode. Using OpenSBI firmware, U-Boot SPL must be compiled for machine mode and U-Boot proper for supervisor mode. To be able to use SPL, boards have to provide a supported SPL boot device. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
82 lines
1.3 KiB
Text
82 lines
1.3 KiB
Text
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* Based on arch/riscv/cpu/u-boot.lds, which is
|
|
* Copyright (C) 2017 Andes Technology Corporation
|
|
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
|
|
*
|
|
* and arch/mips/cpu/u-boot-spl.lds.
|
|
*/
|
|
MEMORY { .spl_mem : ORIGIN = IMAGE_TEXT_BASE, LENGTH = IMAGE_MAX_SIZE }
|
|
MEMORY { .bss_mem : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
|
|
LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
|
|
|
|
OUTPUT_ARCH("riscv")
|
|
ENTRY(_start)
|
|
|
|
SECTIONS
|
|
{
|
|
. = ALIGN(4);
|
|
.text : {
|
|
arch/riscv/cpu/start.o (.text)
|
|
*(.text*)
|
|
} > .spl_mem
|
|
|
|
. = ALIGN(4);
|
|
.rodata : {
|
|
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
|
} > .spl_mem
|
|
|
|
. = ALIGN(4);
|
|
.data : {
|
|
*(.data*)
|
|
} > .spl_mem
|
|
. = ALIGN(4);
|
|
|
|
.got : {
|
|
__got_start = .;
|
|
*(.got.plt) *(.got)
|
|
__got_end = .;
|
|
} > .spl_mem
|
|
|
|
. = ALIGN(4);
|
|
|
|
.u_boot_list : {
|
|
KEEP(*(SORT(.u_boot_list*)));
|
|
} > .spl_mem
|
|
|
|
. = ALIGN(4);
|
|
|
|
.binman_sym_table : {
|
|
__binman_sym_start = .;
|
|
KEEP(*(SORT(.binman_sym*)));
|
|
__binman_sym_end = .;
|
|
} > .spl_mem
|
|
|
|
. = ALIGN(4);
|
|
|
|
/DISCARD/ : { *(.rela.plt*) }
|
|
.rela.dyn : {
|
|
__rel_dyn_start = .;
|
|
*(.rela*)
|
|
__rel_dyn_end = .;
|
|
} > .spl_mem
|
|
|
|
. = ALIGN(4);
|
|
|
|
.dynsym : {
|
|
__dyn_sym_start = .;
|
|
*(.dynsym)
|
|
__dyn_sym_end = .;
|
|
} > .spl_mem
|
|
|
|
. = ALIGN(4);
|
|
|
|
_end = .;
|
|
|
|
.bss : {
|
|
__bss_start = .;
|
|
*(.bss*)
|
|
. = ALIGN(4);
|
|
__bss_end = .;
|
|
} > .bss_mem
|
|
}
|