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https://github.com/AsahiLinux/u-boot
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384e2d396c
Currently, only the 1st SATA port is powered up (by GPIO1 12). Add GPIO1 13 in board initialization to power up the 2nd SATA port. Note that this patch depends on the initial add-support patch: https://patchwork.ozlabs.org/project/uboot/patch/20230201231306.7010-1-mibodhi@gmail.com/ Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
126 lines
3.9 KiB
C
126 lines
3.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2023 Tony Dinh <mibodhi@gmail.com>
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*
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*/
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#include <i2c.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <linux/bitops.h>
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#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
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#include <../serdes/a38x/high_speed_env_spec.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Those N2350_GPP_xx values and defines in board_serdes_map, and board_topology_map
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* are taken from the Marvell U-Boot version "u-boot-a38x-2015T1_p18_Thecus"
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*/
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#define N2350_GPP_OUT_ENA_LOW (~(BIT(20) | BIT(21) | BIT(24)))
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#define N2350_GPP_OUT_ENA_MID (~(BIT(12) | BIT(13) | BIT(16) | BIT(19) | BIT(22)))
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#define N2350_GPP_OUT_VAL_LOW (BIT(21) | BIT(24))
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#define N2350_GPP_OUT_VAL_MID (BIT(0) | BIT(12) | BIT(13))
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#define N2350_GPP_POL_LOW 0x0
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#define N2350_GPP_POL_MID 0x0
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static struct serdes_map board_serdes_map[] = {
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{ SGMII0, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{ SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{ SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{ DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{ USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{ USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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};
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int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
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{
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*serdes_map_array = board_serdes_map;
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*count = ARRAY_SIZE(board_serdes_map);
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return 0;
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}
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/*
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* Define the DDR layout / topology here in the board file. This will
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* be used by the DDR4 init code in the SPL U-Boot version to configure
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* the DDR4 controller.
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*/
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static struct mv_ddr_topology_map board_topology_map = {
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DEBUG_LEVEL_ERROR,
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0x1, /* active interfaces */
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/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
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{ { { {0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0} },
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SPEED_BIN_DDR_1866L, /* speed_bin */
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MV_DDR_DEV_WIDTH_16BIT, /* memory_width - 16 bits */
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MV_DDR_DIE_CAP_4GBIT, /* mem_size - N2350 board has 2x512MB DRAM banks */
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MV_DDR_FREQ_800, /* frequency */
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0, 0, /* cas_wl cas_l */
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MV_DDR_TEMP_LOW, /* temperature */
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MV_DDR_TIM_DEFAULT} }, /* timing */
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BUS_MASK_32BIT, /* Busses mask */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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NOT_COMBINED, /* ddr twin-die combined */
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{ {0} }, /* raw spd data */
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{0} /* timing parameters */
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};
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struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
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{
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/* Return the board topology as defined in the board code */
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return &board_topology_map;
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}
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int board_early_init_f(void)
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{
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/* Those MPP values are taken from the Marvell U-Boot version
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* "u-boot-a38x-2015T1_p18_Thecus"
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*/
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/* Configure MPP */
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writel(0x50111111, MVEBU_MPP_BASE + 0x00); /* MPP0_7 */
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writel(0x00555555, MVEBU_MPP_BASE + 0x04); /* MPP8_15 */
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writel(0x55000000, MVEBU_MPP_BASE + 0x08); /* MPP16_23 */
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writel(0x05050050, MVEBU_MPP_BASE + 0x0c); /* MPP24_31 */
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writel(0x05555555, MVEBU_MPP_BASE + 0x10); /* MPP32_39 */
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writel(0x00000565, MVEBU_MPP_BASE + 0x14); /* MPP40_47 */
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writel(0x00000000, MVEBU_MPP_BASE + 0x18); /* MPP48_55 */
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writel(0x00004444, MVEBU_MPP_BASE + 0x1c); /* MPP56_63 */
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/* Set GPP Out value */
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writel(N2350_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
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writel(N2350_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
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/* Set GPP Polarity */
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writel(N2350_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
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writel(N2350_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
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/* Set GPP Out Enable */
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writel(N2350_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
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writel(N2350_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
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return 0;
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}
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int board_init(void)
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{
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/* Address of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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return 0;
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}
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int board_eth_init(struct bd_info *bis)
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{
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cpu_eth_init(bis); /* Built in controller(s) come first */
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return pci_eth_init(bis);
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}
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