mirror of
https://github.com/AsahiLinux/u-boot
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c8f3402ad2
Add support for the MSC SM2S-IMX8PLUS SMARC Module. Tested in conjunction with the MSC SM2-MB-EP1 Mini-ITX Carrier Board. Signed-off-by: Martyn Welch <martyn.welch@collabora.com> Signed-off-by: Fabio Estevam <festevam@denx.de>
60 lines
1.3 KiB
C
60 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Based on vendor support provided by AVNET Embedded
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*
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* Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH
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* Copyright 2021 General Electric Company
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* Copyright 2021 Collabora Ltd.
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*/
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#include <common.h>
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#include <errno.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx8mp_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm-generic/gpio.h>
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#include <linux/delay.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void setup_fec(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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/* Enable RGMII TX clk output */
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setbits_le32(&gpr->gpr[1], BIT(22));
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}
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static int setup_eqos(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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/* set INTF as RGMII, enable RGMII TXC clock */
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clrsetbits_le32(&gpr->gpr[1],
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IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
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setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
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return set_clk_eqos(ENET_125MHZ);
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}
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int board_phy_config(struct phy_device *phydev)
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{
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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int board_init(void)
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{
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setup_fec();
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setup_eqos();
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return 0;
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}
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