mirror of
https://github.com/AsahiLinux/u-boot
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72fa467988
gen_atmel_mci works on AVR32 as well, so no need to use the legacy mmc driver. This also has the nice side effect of being able to use SDHC cards an those boards. Signed-off-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
198 lines
5.6 KiB
C
198 lines
5.6 KiB
C
/*
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* Copyright (C) 2006 Atmel Corporation
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*
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* Configuration settings for the AVR32 Network Gateway
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/hardware.h>
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#define CONFIG_AVR32
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#define CONFIG_AT32AP
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#define CONFIG_AT32AP7000
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#define CONFIG_MIMC200
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#define CONFIG_MIMC200_EXT_FLASH
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#define CONFIG_SYS_HZ 1000
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/*
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* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
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* frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
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* and the PBA bus to run at 1/4 the PLL frequency.
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*/
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#define CONFIG_PLL
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#define CONFIG_SYS_POWER_MANAGER
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#define CONFIG_SYS_OSC0_HZ 10000000
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#define CONFIG_SYS_PLL0_DIV 1
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#define CONFIG_SYS_PLL0_MUL 15
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#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
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#define CONFIG_SYS_CLKDIV_CPU 0
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#define CONFIG_SYS_CLKDIV_HSB 1
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#define CONFIG_SYS_CLKDIV_PBA 2
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#define CONFIG_SYS_CLKDIV_PBB 1
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/* Reserve VM regions for SDRAM, NOR flash and FRAM */
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#define CONFIG_SYS_NR_VM_REGIONS 3
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/*
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* The PLLOPT register controls the PLL like this:
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* icp = PLLOPT<2>
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* ivco = PLLOPT<1:0>
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*
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* We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
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*/
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#define CONFIG_SYS_PLL0_OPT 0x04
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#define CONFIG_USART_BASE ATMEL_BASE_USART1
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#define CONFIG_USART_ID 1
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#define CONFIG_MIMC200_DBGLINK 1
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/* User serviceable stuff */
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#define CONFIG_DOS_PARTITION
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_STACKSIZE (2048)
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTARGS \
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"root=/dev/mtdblock1 rootfstype=jffs2 fbmem=512k console=ttyS1"
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#define CONFIG_BOOTCOMMAND \
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"fsload boot/uImage; bootm"
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#define CONFIG_SILENT_CONSOLE /* enable silent startup */
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#define CONFIG_DISABLE_CONSOLE /* disable console */
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#define CONFIG_SYS_DEVICE_NULLDEV /* include nulldev device */
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#define CONFIG_LCD 1
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/*
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* Only interrupt autoboot if <space> is pressed. Otherwise, garbage
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* data on the serial line may interrupt the boot sequence.
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*/
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#define CONFIG_BOOTDELAY 0
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#define CONFIG_ZERO_BOOTDELAY_CHECK
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#define CONFIG_AUTOBOOT
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/*
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* After booting the board for the first time, new ethernet addresses
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* should be generated and assigned to the environment variables
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* "ethaddr" and "eth1addr". This is normally done during production.
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*/
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#define CONFIG_OVERWRITE_ETHADDR_ONCE
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/*
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* BOOTP/DHCP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_MMC
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#define CONFIG_CMD_NET
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#define CONFIG_ATMEL_USART
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#define CONFIG_MACB
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#define CONFIG_PORTMUX_PIO
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#define CONFIG_SYS_NR_PIOS 5
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#define CONFIG_SYS_HSDRAMC
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#define CONFIG_MMC
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#define CONFIG_GENERIC_ATMEL_MCI
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#define CONFIG_GENERIC_MMC
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#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1
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#if defined(CONFIG_LCD)
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#define CONFIG_CMD_BMP
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#define CONFIG_ATMEL_LCD 1
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#define LCD_BPP LCD_COLOR16
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#define CONFIG_BMP_16BPP 1
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#define CONFIG_FB_ADDR 0x10600000
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#define CONFIG_WHITE_ON_BLACK 1
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#define CONFIG_VIDEO_BMP_GZIP 1
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#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE 262144
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#define CONFIG_ATMEL_LCD_BGR555 1
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
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#define CONFIG_SPLASH_SCREEN 1
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#endif
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#define CONFIG_SYS_DCACHE_LINESZ 32
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#define CONFIG_SYS_ICACHE_LINESZ 32
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_BASE 0x00000000
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#define CONFIG_SYS_FLASH_SIZE 0x800000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 135
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_TEXT_BASE 0x00000000
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#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
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#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
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#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
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#define CONFIG_SYS_FRAM_BASE 0x08000000
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#define CONFIG_SYS_FRAM_SIZE 0x20000
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SIZE 65536
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
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#define CONFIG_SYS_MALLOC_LEN (1024*1024)
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#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
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/* Allow 4MB for the kernel run-time image */
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#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
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#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
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/* Other configuration settings that shouldn't have to change all that often */
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#define CONFIG_SYS_PROMPT "U-Boot> "
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
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#endif /* __CONFIG_H */
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