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https://github.com/AsahiLinux/u-boot
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4dbdc84754
Pull in dtb updates for the am654 base board from v6.7-rc1 of Linux Tested-by: Tom Rini <trini@konsulko.com> Signed-off-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com>
122 lines
2.3 KiB
Text
122 lines
2.3 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for AM6 SoC family in Quad core configuration
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*
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include "k3-am65.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0: cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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};
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cluster1: cluster1 {
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core0 {
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cpu = <&cpu2>;
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};
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core1 {
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cpu = <&cpu3>;
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};
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};
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};
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53";
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reg = <0x000>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&L2_0>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53";
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reg = <0x001>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&L2_0>;
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};
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cpu2: cpu@100 {
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compatible = "arm,cortex-a53";
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reg = <0x100>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&L2_1>;
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};
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cpu3: cpu@101 {
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compatible = "arm,cortex-a53";
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reg = <0x101>;
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device_type = "cpu";
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&L2_1>;
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};
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-sets = <512>;
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next-level-cache = <&msmc_l3>;
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};
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L2_1: l2-cache1 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-sets = <512>;
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next-level-cache = <&msmc_l3>;
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};
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msmc_l3: l3-cache0 {
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compatible = "cache";
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cache-level = <3>;
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cache-unified;
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};
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thermal_zones: thermal-zones {
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#include "k3-am654-industrial-thermal.dtsi"
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};
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};
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