u-boot/arch/arm/mach-omap2/omap-cache.c
Masahiro Yamada b75d8dc564 treewide: convert bd_t to struct bd_info by coccinelle
The Linux coding style guide (Documentation/process/coding-style.rst)
clearly says:

  It's a **mistake** to use typedef for structures and pointers.

Besides, using typedef for structures is annoying when you try to make
headers self-contained.

Let's say you have the following function declaration in a header:

  void foo(bd_t *bd);

This is not self-contained since bd_t is not defined.

To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h>

  #include <asm/u-boot.h>
  void foo(bd_t *bd);

Then, the include direcective pulls in more bloat needlessly.

If you use 'struct bd_info' instead, it is enough to put a forward
declaration as follows:

  struct bd_info;
  void foo(struct bd_info *bd);

Right, typedef'ing bd_t is a mistake.

I used coccinelle to generate this commit.

The semantic patch that makes this change is as follows:

  <smpl>
  @@
  typedef bd_t;
  @@
  -bd_t
  +struct bd_info
  </smpl>

Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2020-07-17 09:30:13 -04:00

82 lines
1.7 KiB
C

// SPDX-License-Identifier: GPL-2.0+
/*
*
* Common functions for OMAP4/5 based boards
*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Author :
* Aneesh V <aneesh@ti.com>
* Steve Sakoman <steve@sakoman.com>
*/
#include <common.h>
#include <cpu_func.h>
#include <log.h>
#include <asm/cache.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Without LPAE short descriptors are used
* Set C - Cache Bit3
* Set B - Buffer Bit2
* The last 2 bits set to 0b10
* Do Not set XN bit4
* So value is 0xe
*
* With LPAE cache configuration happens via MAIR0 register
* AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF.
* 0xFF maps to Cache writeback with Read and Write Allocate set
* The bits[1:0] should have the value 0b01 for the first level
* descriptor.
* So the value is 0xd
*/
#ifdef CONFIG_ARMV7_LPAE
#define ARMV7_DCACHE_POLICY DCACHE_WRITEALLOC
#else
#define ARMV7_DCACHE_POLICY DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK
#endif
#define ARMV7_DOMAIN_CLIENT 1
#define ARMV7_DOMAIN_MASK (0x3 << 0)
void enable_caches(void)
{
/* Enable I cache if not enabled */
if (!icache_status())
icache_enable();
dcache_enable();
}
void dram_bank_mmu_setup(int bank)
{
struct bd_info *bd = gd->bd;
int i;
u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
u32 end = start + size;
debug("%s: bank: %d\n", __func__, bank);
for (i = start; i < end; i++)
set_section_dcache(i, ARMV7_DCACHE_POLICY);
}
void arm_init_domains(void)
{
u32 reg;
reg = get_dacr();
/*
* Set DOMAIN to client access so that all permissions
* set in pagetables are validated by the mmu.
*/
reg &= ~ARMV7_DOMAIN_MASK;
reg |= ARMV7_DOMAIN_CLIENT;
set_dacr(reg);
}