mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-30 08:31:03 +00:00
484a878273
The SSP2 clock is at bit 6 in the register, so the value is 0x40 unlike the current 0x70 which enables the clock of UART2, SSP1 and SSP2. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Acked-by: Stefan Roese <sr@denx.de> |
||
---|---|---|
.. | ||
clk.h | ||
gpio.h | ||
hardware.h | ||
spr_defs.h | ||
spr_emi.h | ||
spr_gpt.h | ||
spr_misc.h | ||
spr_ssp.h | ||
spr_syscntl.h |