mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-27 05:23:34 +00:00
f89d6133ee
Moved CONFIG_SPL_TEXT_BASE to common/spl/Kconfig and migrate existing values. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Re-run migration] Signed-off-by: Tom Rini <trini@konsulko.com>
127 lines
3.1 KiB
C
127 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Allied Telesis Labs
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*/
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#ifndef _CONFIG_X530_H
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#define _CONFIG_X530_H
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/*
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* High Level Configuration Options (easy to change)
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*/
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#define CONFIG_DISPLAY_BOARDINFO_LATE
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#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
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/*
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* NS16550 Configuration
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*/
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
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#if !defined(CONFIG_DM_SERIAL)
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#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE
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#endif
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/*
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* Serial Port configuration
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* The following definitions let you select what serial you want to use
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* for your console driver.
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*/
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#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
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/*
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* Commands configuration
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*/
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#define CONFIG_CMD_PCI
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/* NAND */
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#define CONFIG_SYS_NAND_USE_FLASH_BBT
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define BBT_CUSTOM_SCAN
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#define BBT_CUSTOM_SCAN_PAGE 0
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#define BBT_CUSTOM_SCAN_POSITION 2048
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/* SPI NOR flash default params, used by sf commands */
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#define MTDIDS_DEFAULT "nand0=nand"
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#define MTDPARTS_DEFAULT "mtdparts=nand:240M(user),8M(errlog),8M(nand-bbt)"
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#define MTDPARTS_MTDOOPS "errlog"
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/* Partition support */
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/* Additional FS support/configuration */
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/* USB/EHCI configuration */
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#define CONFIG_EHCI_IS_TDI
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/* Environment in SPI NOR flash */
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#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
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#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
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#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
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#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
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#define CONFIG_PHY_MARVELL /* there is a marvell phy */
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#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
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/* PCIe support */
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_PCI_SCAN_SHOW
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#endif
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/* NAND */
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#define CONFIG_SYS_NAND_USE_FLASH_BBT
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#define CONFIG_CMD_UBI
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#define CONFIG_CMD_UBIFS
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#define CONFIG_LZO
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#define CONFIG_MTD_DEVICE
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_SYS_MALLOC_LEN (4 << 20)
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#include <asm/arch/config.h>
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/*
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* Other required minimal configurations
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*/
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#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
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#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
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#define CONFIG_SYS_ALT_MEMTEST
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/* Keep device tree and initrd in low memory so the kernel can access them */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"fdt_high=0x10000000\0" \
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"initrd_high=0x10000000\0"
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#define CONFIG_SYS_LOAD_ADDR 0x1000000
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#define CONFIG_UBI_PART user
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#define CONFIG_UBIFS_VOLUME user
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/* SPL */
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/* Defines for SPL */
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#define CONFIG_SPL_SIZE (140 << 10)
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#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030)
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#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE)
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#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MALLOC_SIMPLE
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#endif
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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/* SPL related SPI defines */
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
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#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
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#endif /* _CONFIG_X530_H */
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