mirror of
https://github.com/AsahiLinux/u-boot
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a86ac9540e
Since commit 0e7368c6c4 (kbuild: prepare for moving headers into
mach-*/include/mach), we can replace #include <asm/arch/*.h> with
<mach/*.h> so we do not need to create the symbolic link during the
build.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
189 lines
4.1 KiB
C
189 lines
4.1 KiB
C
/*
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* Copyright (C) 2011-2014 Panasonic Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <mach/sc-regs.h>
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#include <mach/sg-regs.h>
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#undef DPLL_SSC_RATE_1PER
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static void dpll_init(void)
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{
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u32 tmp;
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/*
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* Set Frequency
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* Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
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* to FOUT (DPLLCTRL.bit[29:20])
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*/
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tmp = readl(SC_DPLLCTRL);
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tmp &= ~0x000f0000;
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#if CONFIG_DDR_FREQ == 1600
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tmp |= 0x000c0000;
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#elif CONFIG_DDR_FREQ == 1333
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tmp |= 0x000d0000;
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#else
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# error "Unknown frequency"
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#endif
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#if defined(DPLL_SSC_RATE_1PER)
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tmp &= ~SC_DPLLCTRL_SSC_RATE;
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#else
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tmp |= SC_DPLLCTRL_SSC_RATE;
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#endif
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writel(tmp, SC_DPLLCTRL);
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tmp = readl(SC_DPLLCTRL2);
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tmp |= SC_DPLLCTRL2_NRSTDS;
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writel(tmp, SC_DPLLCTRL2);
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}
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static void upll_init(void)
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{
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u32 tmp, clk_mode_upll, clk_mode_axosel;
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tmp = readl(SG_PINMON0);
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clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
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clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
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/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
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tmp = readl(SC_UPLLCTRL);
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tmp &= ~0x18000000;
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writel(tmp, SC_UPLLCTRL);
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if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
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if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
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clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
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/* AXO: 25MHz */
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tmp &= ~0x07ffffff;
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tmp |= 0x0228f5c0;
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} else {
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/* AXO: default 24.576MHz */
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tmp &= ~0x07ffffff;
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tmp |= 0x02328000;
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}
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}
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writel(tmp, SC_UPLLCTRL);
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/* set 1 to K_LD(UPLLCTRL.bit[27]) */
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tmp |= 0x08000000;
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writel(tmp, SC_UPLLCTRL);
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/* wait 10 usec */
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udelay(10);
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/* set 1 to SNRT(UPLLCTRL.bit[28]) */
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tmp |= 0x10000000;
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writel(tmp, SC_UPLLCTRL);
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}
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static void vpll_init(void)
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{
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u32 tmp, clk_mode_axosel;
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tmp = readl(SG_PINMON0);
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clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
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/* set 1 to VPLA27WP and VPLA27WP */
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tmp = readl(SC_VPLL27ACTRL);
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tmp |= 0x00000001;
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writel(tmp, SC_VPLL27ACTRL);
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tmp = readl(SC_VPLL27BCTRL);
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tmp |= 0x00000001;
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writel(tmp, SC_VPLL27BCTRL);
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/* Set 0 to VPLA_K_LD and VPLB_K_LD */
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tmp = readl(SC_VPLL27ACTRL3);
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tmp &= ~0x10000000;
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writel(tmp, SC_VPLL27ACTRL3);
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tmp = readl(SC_VPLL27BCTRL3);
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tmp &= ~0x10000000;
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writel(tmp, SC_VPLL27BCTRL3);
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/* Set 0 to VPLA_SNRST and VPLB_SNRST */
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tmp = readl(SC_VPLL27ACTRL2);
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tmp &= ~0x10000000;
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writel(tmp, SC_VPLL27ACTRL2);
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tmp = readl(SC_VPLL27BCTRL2);
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tmp &= ~0x10000000;
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writel(tmp, SC_VPLL27BCTRL2);
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/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
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tmp = readl(SC_VPLL27ACTRL2);
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tmp &= ~0x0000007f;
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tmp |= 0x00000020;
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writel(tmp, SC_VPLL27ACTRL2);
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tmp = readl(SC_VPLL27BCTRL2);
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tmp &= ~0x0000007f;
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tmp |= 0x00000020;
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writel(tmp, SC_VPLL27BCTRL2);
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if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
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clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
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/* AXO: 25MHz */
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tmp = readl(SC_VPLL27ACTRL3);
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tmp &= ~0x000fffff;
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tmp |= 0x00066664;
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writel(tmp, SC_VPLL27ACTRL3);
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tmp = readl(SC_VPLL27BCTRL3);
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tmp &= ~0x000fffff;
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tmp |= 0x00066664;
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writel(tmp, SC_VPLL27BCTRL3);
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} else {
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/* AXO: default 24.576MHz */
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tmp = readl(SC_VPLL27ACTRL3);
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tmp &= ~0x000fffff;
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tmp |= 0x000f5800;
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writel(tmp, SC_VPLL27ACTRL3);
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tmp = readl(SC_VPLL27BCTRL3);
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tmp &= ~0x000fffff;
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tmp |= 0x000f5800;
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writel(tmp, SC_VPLL27BCTRL3);
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}
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/* Set 1 to VPLA_K_LD and VPLB_K_LD */
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tmp = readl(SC_VPLL27ACTRL3);
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tmp |= 0x10000000;
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writel(tmp, SC_VPLL27ACTRL3);
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tmp = readl(SC_VPLL27BCTRL3);
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tmp |= 0x10000000;
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writel(tmp, SC_VPLL27BCTRL3);
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/* wait 10 usec */
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udelay(10);
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/* Set 0 to VPLA_SNRST and VPLB_SNRST */
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tmp = readl(SC_VPLL27ACTRL2);
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tmp |= 0x10000000;
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writel(tmp, SC_VPLL27ACTRL2);
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tmp = readl(SC_VPLL27BCTRL2);
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tmp |= 0x10000000;
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writel(tmp, SC_VPLL27BCTRL2);
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/* set 0 to VPLA27WP and VPLA27WP */
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tmp = readl(SC_VPLL27ACTRL);
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tmp &= ~0x00000001;
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writel(tmp, SC_VPLL27ACTRL);
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tmp = readl(SC_VPLL27BCTRL);
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tmp |= ~0x00000001;
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writel(tmp, SC_VPLL27BCTRL);
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}
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void pll_init(void)
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{
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dpll_init();
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upll_init();
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vpll_init();
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/*
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* Wait 500 usec until dpll get stable
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* We wait 10 usec in upll_init() and vpll_init()
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* so 20 usec can be saved here.
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*/
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udelay(480);
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}
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