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https://github.com/AsahiLinux/u-boot
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242d1cd69b
Add a module to configure the tamper and secure violation of the SNVS using the SCU API. The module also adds some commands: - snvs_cfg: Configure the SNVS HP and LP registers - snvs_dgo_cfg: Configure the SNVS DGO bloc if present (8QXP) - tamper_pin_cfg: Change the configuration of the tamper pins - snvs_clear_status: Allow to write to LPSR and LPTDSR to clear status bits Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
136 lines
4.6 KiB
C
136 lines
4.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018 NXP
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*/
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#ifndef _SC_SCI_H
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#define _SC_SCI_H
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#include <asm/arch/sci/types.h>
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#include <asm/arch/sci/svc/misc/api.h>
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#include <asm/arch/sci/svc/pad/api.h>
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#include <asm/arch/sci/svc/pm/api.h>
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#include <asm/arch/sci/svc/rm/api.h>
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#include <asm/arch/sci/svc/seco/api.h>
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#include <asm/arch/sci/rpc.h>
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#include <dt-bindings/soc/imx_rsrc.h>
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#include <linux/errno.h>
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static inline int sc_err_to_linux(sc_err_t err)
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{
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int ret;
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switch (err) {
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case SC_ERR_NONE:
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return 0;
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case SC_ERR_VERSION:
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case SC_ERR_CONFIG:
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case SC_ERR_PARM:
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ret = -EINVAL;
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break;
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case SC_ERR_NOACCESS:
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case SC_ERR_LOCKED:
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case SC_ERR_UNAVAILABLE:
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ret = -EACCES;
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break;
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case SC_ERR_NOTFOUND:
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case SC_ERR_NOPOWER:
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ret = -ENODEV;
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break;
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case SC_ERR_IPC:
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ret = -EIO;
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break;
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case SC_ERR_BUSY:
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ret = -EBUSY;
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break;
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case SC_ERR_FAIL:
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ret = -EIO;
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break;
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default:
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ret = 0;
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break;
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}
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debug("%s %d %d\n", __func__, err, ret);
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return ret;
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}
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/* PM API*/
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int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
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sc_pm_power_mode_t mode);
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int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
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sc_pm_power_mode_t *mode);
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int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
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sc_pm_clock_rate_t *rate);
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int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
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sc_pm_clock_rate_t *rate);
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int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
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sc_bool_t enable, sc_bool_t autog);
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int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
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sc_pm_clk_parent_t parent);
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int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
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sc_faddr_t address);
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sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt);
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int sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource);
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/* MISC API */
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int sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource,
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sc_ctrl_t ctrl, u32 val);
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int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl,
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u32 *val);
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void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev);
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void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status);
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void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit);
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int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val);
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int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp,
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s16 *celsius, s8 *tenths);
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/* RM API */
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sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr);
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int sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, sc_faddr_t addr_start,
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sc_faddr_t addr_end);
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int sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr,
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sc_rm_pt_t pt, sc_rm_perm_t perm);
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int sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, sc_faddr_t *addr_start,
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sc_faddr_t *addr_end);
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sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource);
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int sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure,
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sc_bool_t isolated, sc_bool_t restricted,
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sc_bool_t grant, sc_bool_t coherent);
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int sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt);
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int sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt);
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int sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent);
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int sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource);
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int sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad);
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sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad);
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int sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource,
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sc_rm_pt_t *pt);
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/* PAD API */
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int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val);
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int sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val);
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/* SMMU API */
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int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid);
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/* SECO API */
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int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd,
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sc_faddr_t addr);
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int sc_seco_forward_lifecycle(sc_ipc_t ipc, u32 change);
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int sc_seco_chip_info(sc_ipc_t ipc, u16 *lc, u16 *monotonic, u32 *uid_l,
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u32 *uid_h);
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void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit);
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int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event);
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int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr,
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sc_faddr_t export_addr, u16 max_size);
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int sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, u16 dst_size);
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int sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, u8 size, u8 lock);
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int sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr,
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u16 msg_size, sc_faddr_t dst_addr, u16 dst_size);
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int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data);
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int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access,
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u32 *data0, u32 *data1, u32 *data2, u32 *data3,
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u32 *data4, u8 size);
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#endif
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