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https://github.com/AsahiLinux/u-boot
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074cff0d28
Add support for S3C44B0 processor and DAVE B2 board * Patch by Steven Scholz, 20 Feb 2004: - Add support for MII commands on AT91RM9200 boards - some cleanup in AT91RM9200 ethernet code
209 lines
6.9 KiB
C
209 lines
6.9 KiB
C
/*
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* (C) Copyright 2004
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* DAVE Srl
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*
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* http://www.dave-tech.it
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* http://www.wawnet.biz
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* mailto:info@wawnet.biz
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*
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* Configuation settings for the B2 board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* If we are developing, we might want to start armboot from ram
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* so we MUST NOT initialize critical regs like mem-timing ...
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*/
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#define CONFIG_INIT_CRITICAL /* undef for developing */
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_ARM7 1 /* This is a ARM7 CPU */
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#define CONFIG_B2 1 /* on an B2 Board */
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#define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */
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#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
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#define CONFIG_S3C44B0_CLOCK_SPEED 75 /* we have a 75Mhz S3C44B0*/
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#undef CONFIG_USE_IRQ /* don't need them anymore */
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/*
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* Size of malloc() pool
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*/
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
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#define CFG_ENV_SIZE 1024 /* 1024 bytes may be used for env vars*/
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#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024 )
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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/*
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* Hardware drivers
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*/
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#define CONFIG_DRIVER_LAN91C96
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#define CONFIG_LAN91C96_BASE 0x04000300 /* base address */
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#define CONFIG_SMC_USE_32_BIT
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#undef CONFIG_SHOW_ACTIVITY
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#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
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/*
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* select serial console configuration
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*/
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#define CONFIG_SERIAL1 1 /* we use Serial line 1 */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_DATE | \
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CFG_CMD_ELF | \
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CFG_CMD_EEPROM | \
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CFG_CMD_I2C )
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#define CONFIG_BOOTDELAY 5
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#define CONFIG_ETHADDR 00:50:c2:1e:af:fb
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#define CONFIG_BOOTARGS "setenv bootargs root=/dev/ram ip=192.168.0.70:::::eth0:off \
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ether=25,0,0,0,eth0 ethaddr=00:50:c2:1e:af:fb"
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#define CONFIG_NETMASK 255.255.0.0
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#define CONFIG_IPADDR 192.168.0.70
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#define CONFIG_SERVERIP 192.168.0.23
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#define CONFIG_BOOTFILE "B2-rootfs/usr/B2-zImage.u-boot"
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#define CONFIG_BOOTCOMMAND "bootm 20000 f0000"
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0C400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C800000 /* 4 ... 8 MB in DRAM */
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#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
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#define CFG_LOAD_ADDR 0x0c700000 /* default load address */
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#define CFG_HZ 1000 /* 1 kHz */
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/* valid baudrates */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*-----------------------------------------------------------------------
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
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#endif
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */
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#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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#define PHYS_FLASH_SIZE 0x00400000 /* 4 MB */
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#define CFG_FLASH_BASE PHYS_FLASH_1
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
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#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
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#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
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/*
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* The following defines are added for buggy IOP480 byte interface.
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* All other boards should use the standard values (CPCI405 etc.)
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*/
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#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
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#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
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#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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/*-----------------------------------------------------------------------
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* Environment Variable setup
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*/
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#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
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#define CFG_ENV_OFFSET 0x0 /* environment starts at the beginning of the EEPROM */
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/*-----------------------------------------------------------------------
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* I2C EEPROM (STM24C02W6) for environment
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*/
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#define CONFIG_HARD_I2C /* I2c with hardware support */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0xFE
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#define CFG_I2C_EEPROM_ADDR 0xA8 /* EEPROM STM24C02W6 */
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#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
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/* mask of address bits that overflow into the "EEPROM chip address" */
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/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07*/
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#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
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/* 16 byte page write mode using*/
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/* last 4 bits of the address */
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
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#define CFG_EEPROM_PAGE_WRITE_ENABLE
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/* Flash banks JFFS2 should use */
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/*
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#define CFG_JFFS2_FIRST_BANK 0
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#define CFG_JFFS2_FIRST_SECTOR 2
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#define CFG_JFFS2_NUM_BANKS 1
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*/
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/*
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Linux TAGs (see lib_arm/armlinux.c)
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*/
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#define CONFIG_CMDLINE_TAG
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#undef CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#endif /* __CONFIG_H */
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