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https://github.com/AsahiLinux/u-boot
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81e33f4b65
Until now, the SoC selection for the ARCH_MVEBU platforms has been done in the config header. Using CONFIG_ARMADA_XP in a non-clear way. As it needed to get selected for AXP and A38x based boards. This patch now changes this to move the SoC selection to Kconfig. And also uses CONFIG_ARCH_MVEBU as a common define for both AXP and A38x. This makes things a bit clearer - especially for new board additions. Additionally the defines CONFIG_SYS_MVEBU_DDR_AXP and CONFIG_SYS_MVEBU_DDR_A38X are replaced with the already available CONFIG_ARMADA_38X and CONFIG_ARMADA_XP. And CONFIG_DDR3 is removed, as its not referenced anywhere. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
149 lines
3.9 KiB
C
149 lines
3.9 KiB
C
/*
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* Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _CONFIG_DB_MV7846MP_GP_H
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#define _CONFIG_DB_MV7846MP_GP_H
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/*
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* High Level Configuration Options (easy to change)
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*/
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#define CONFIG_DB_784MP_GP /* Board target name for DDR training */
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#define CONFIG_DISPLAY_BOARDINFO_LATE
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/*
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* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
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* for DDR ECC byte filling in the SPL before loading the main
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* U-Boot into it.
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*/
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#define CONFIG_SYS_TEXT_BASE 0x00800000
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#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
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/*
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* Commands configuration
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*/
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#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_ENV
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_EXT4
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_FS_GENERIC
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SATA
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#define CONFIG_CMD_SF
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#define CONFIG_CMD_SPI
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#define CONFIG_CMD_TFTPPUT
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#define CONFIG_CMD_TIME
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MVTWSI
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#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
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#define CONFIG_SYS_I2C_SLAVE 0x0
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#define CONFIG_SYS_I2C_SPEED 100000
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/* USB/EHCI configuration */
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#define CONFIG_EHCI_IS_TDI
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
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/* SPI NOR flash default params, used by sf commands */
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#define CONFIG_SF_DEFAULT_SPEED 1000000
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
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/* Environment in SPI NOR flash */
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
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#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
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#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
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#define CONFIG_PHY_MARVELL /* there is a marvell phy */
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#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
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#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
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#define CONFIG_SYS_ALT_MEMTEST
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/* SATA support */
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#define CONFIG_SYS_SATA_MAX_DEVICE 2
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#define CONFIG_SATA_MV
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#define CONFIG_LIBATA
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#define CONFIG_LBA48
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#define CONFIG_EFI_PARTITION
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#define CONFIG_DOS_PARTITION
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/* Additional FS support/configuration */
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#define CONFIG_SUPPORT_VFAT
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/* PCIe support */
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_PCI
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#define CONFIG_PCI_MVEBU
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#define CONFIG_PCI_PNP
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#define CONFIG_PCI_SCAN_SHOW
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#endif
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/* NAND */
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#define CONFIG_SYS_NAND_USE_FLASH_BBT
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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/*
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* mv-common.h should be defined after CMD configs since it used them
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* to enable certain macros
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*/
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#include "mv-common.h"
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/*
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* Memory layout while starting into the bin_hdr via the
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* BootROM:
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*
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* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
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* 0x4000.4030 bin_hdr start address
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* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
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* 0x4007.fffc BootROM stack top
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*
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* The address space between 0x4007.fffc and 0x400f.fff is not locked in
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* L2 cache thus cannot be used.
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*/
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/* SPL */
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/* Defines for SPL */
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_TEXT_BASE 0x40004030
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#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
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#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
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#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MALLOC_SIMPLE
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#endif
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_I2C_SUPPORT
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/* SPL related SPI defines */
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#define CONFIG_SPL_SPI_SUPPORT
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#define CONFIG_SPL_SPI_FLASH_SUPPORT
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SPL_SPI_BUS 0
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#define CONFIG_SPL_SPI_CS 0
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
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#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
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/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
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#define CONFIG_SPD_EEPROM 0x4e
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#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
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#endif /* _CONFIG_DB_MV7846MP_GP_H */
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