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f7d4cab1b3
As per driver model we should enumerate plat structure only in of_to_plat() and should be used only in probe(). Copy required plat structure info into priv structure in probe() and use priv structure across the driver. So replace plat with priv structure across the driver. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220824113847.7482-4-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
309 lines
11 KiB
C
309 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2012
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* Altera Corporation <www.altera.com>
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*/
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#ifndef __CADENCE_QSPI_H__
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#define __CADENCE_QSPI_H__
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#include <reset.h>
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#include <linux/mtd/spi-nor.h>
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#include <spi-mem.h>
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#define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0)
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#define CQSPI_NO_DECODER_MAX_CS 4
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#define CQSPI_DECODER_MAX_CS 16
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#define CQSPI_READ_CAPTURE_MAX_DELAY 16
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#define CQSPI_REG_POLL_US 1 /* 1us */
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#define CQSPI_REG_RETRY 10000
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#define CQSPI_POLL_IDLE_RETRY 3
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/* Transfer mode */
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#define CQSPI_INST_TYPE_SINGLE 0
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#define CQSPI_INST_TYPE_DUAL 1
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#define CQSPI_INST_TYPE_QUAD 2
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#define CQSPI_INST_TYPE_OCTAL 3
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#define CQSPI_STIG_DATA_LEN_MAX 8
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#define CQSPI_DUMMY_CLKS_PER_BYTE 8
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#define CQSPI_DUMMY_BYTES_MAX 4
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#define CQSPI_DUMMY_CLKS_MAX 31
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/****************************************************************************
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* Controller's configuration and status register (offset from QSPI_BASE)
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****************************************************************************/
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#define CQSPI_REG_CONFIG 0x00
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#define CQSPI_REG_CONFIG_ENABLE BIT(0)
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#define CQSPI_REG_CONFIG_CLK_POL BIT(1)
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#define CQSPI_REG_CONFIG_CLK_PHA BIT(2)
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#define CQSPI_REG_CONFIG_PHY_ENABLE_MASK BIT(3)
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#define CQSPI_REG_CONFIG_DIRECT BIT(7)
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#define CQSPI_REG_CONFIG_DECODE BIT(9)
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#define CQSPI_REG_CONFIG_ENBL_DMA BIT(15)
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#define CQSPI_REG_CONFIG_XIP_IMM BIT(18)
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#define CQSPI_REG_CONFIG_DTR_PROT_EN_MASK BIT(24)
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#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
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#define CQSPI_REG_CONFIG_BAUD_LSB 19
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#define CQSPI_REG_CONFIG_DTR_PROTO BIT(24)
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#define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30)
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#define CQSPI_REG_CONFIG_IDLE_LSB 31
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#define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
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#define CQSPI_REG_CONFIG_BAUD_MASK 0xF
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#define CQSPI_REG_RD_INSTR 0x04
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#define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
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#define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
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#define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
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#define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
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#define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
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#define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
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#define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
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#define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
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#define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
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#define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
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#define CQSPI_REG_WR_INSTR 0x08
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#define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
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#define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12
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#define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16
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#define CQSPI_REG_DELAY 0x0C
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#define CQSPI_REG_DELAY_TSLCH_LSB 0
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#define CQSPI_REG_DELAY_TCHSH_LSB 8
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#define CQSPI_REG_DELAY_TSD2D_LSB 16
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#define CQSPI_REG_DELAY_TSHSL_LSB 24
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#define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
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#define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
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#define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
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#define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
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#define CQSPI_REG_RD_DATA_CAPTURE 0x10
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#define CQSPI_REG_RD_DATA_CAPTURE_BYPASS BIT(0)
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#define CQSPI_REG_READCAPTURE_DQS_ENABLE BIT(8)
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#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB 1
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#define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK 0xF
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#define CQSPI_REG_SIZE 0x14
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#define CQSPI_REG_SIZE_ADDRESS_LSB 0
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#define CQSPI_REG_SIZE_PAGE_LSB 4
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#define CQSPI_REG_SIZE_BLOCK_LSB 16
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#define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
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#define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
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#define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
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#define CQSPI_REG_SRAMPARTITION 0x18
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#define CQSPI_REG_INDIRECTTRIGGER 0x1C
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#define CQSPI_REG_REMAP 0x24
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#define CQSPI_REG_MODE_BIT 0x28
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#define CQSPI_REG_SDRAMLEVEL 0x2C
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#define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
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#define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
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#define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
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#define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
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#define CQSPI_REG_WR_COMPLETION_CTRL 0x38
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#define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14)
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#define CQSPI_REG_IRQSTATUS 0x40
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#define CQSPI_REG_IRQMASK 0x44
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#define CQSPI_REG_INDIRECTRD 0x60
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#define CQSPI_REG_INDIRECTRD_START BIT(0)
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#define CQSPI_REG_INDIRECTRD_CANCEL BIT(1)
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#define CQSPI_REG_INDIRECTRD_INPROGRESS BIT(2)
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#define CQSPI_REG_INDIRECTRD_DONE BIT(5)
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#define CQSPI_REG_INDIRECTRDWATERMARK 0x64
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#define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
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#define CQSPI_REG_INDIRECTRDBYTES 0x6C
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#define CQSPI_REG_CMDCTRL 0x90
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#define CQSPI_REG_CMDCTRL_EXECUTE BIT(0)
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#define CQSPI_REG_CMDCTRL_INPROGRESS BIT(1)
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#define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
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#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
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#define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
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#define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
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#define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
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#define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
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#define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
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#define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
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#define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F
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#define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
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#define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
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#define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
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#define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF
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#define CQSPI_REG_INDIRECTWR 0x70
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#define CQSPI_REG_INDIRECTWR_START BIT(0)
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#define CQSPI_REG_INDIRECTWR_CANCEL BIT(1)
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#define CQSPI_REG_INDIRECTWR_INPROGRESS BIT(2)
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#define CQSPI_REG_INDIRECTWR_DONE BIT(5)
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#define CQSPI_REG_INDIRECTWRWATERMARK 0x74
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#define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
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#define CQSPI_REG_INDIRECTWRBYTES 0x7C
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#define CQSPI_REG_CMDADDRESS 0x94
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#define CQSPI_REG_CMDREADDATALOWER 0xA0
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#define CQSPI_REG_CMDREADDATAUPPER 0xA4
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#define CQSPI_REG_CMDWRITEDATALOWER 0xA8
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#define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
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#define CQSPI_REG_OP_EXT_LOWER 0xE0
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#define CQSPI_REG_OP_EXT_READ_LSB 24
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#define CQSPI_REG_OP_EXT_WRITE_LSB 16
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#define CQSPI_REG_OP_EXT_STIG_LSB 0
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#define CQSPI_REG_PHY_CONFIG 0xB4
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#define CQSPI_REG_PHY_CONFIG_RESET_FLD_MASK 0x40000000
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#define CQSPI_DMA_DST_ADDR_REG 0x1800
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#define CQSPI_DMA_DST_SIZE_REG 0x1804
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#define CQSPI_DMA_DST_STS_REG 0x1808
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#define CQSPI_DMA_DST_CTRL_REG 0x180C
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#define CQSPI_DMA_DST_I_STS_REG 0x1814
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#define CQSPI_DMA_DST_I_ENBL_REG 0x1818
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#define CQSPI_DMA_DST_I_DISBL_REG 0x181C
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#define CQSPI_DMA_DST_CTRL2_REG 0x1824
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#define CQSPI_DMA_DST_ADDR_MSB_REG 0x1828
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#define CQSPI_DMA_SRC_RD_ADDR_REG 0x1000
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#define CQSPI_REG_DMA_PERIPH_CFG 0x20
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#define CQSPI_REG_INDIR_TRIG_ADDR_RANGE 0x80
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#define CQSPI_DFLT_INDIR_TRIG_ADDR_RANGE 6
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#define CQSPI_DFLT_DMA_PERIPH_CFG 0x602
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#define CQSPI_DFLT_DST_CTRL_REG_VAL 0xF43FFA00
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#define CQSPI_DMA_DST_I_STS_DONE BIT(1)
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#define CQSPI_DMA_TIMEOUT 10000000
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#define CQSPI_REG_IS_IDLE(base) \
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((readl((base) + CQSPI_REG_CONFIG) >> \
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CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
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#define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \
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(((readl((reg_base) + CQSPI_REG_SDRAMLEVEL)) >> \
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CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
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#define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \
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(((readl((reg_base) + CQSPI_REG_SDRAMLEVEL)) >> \
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CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
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struct cadence_spi_plat {
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unsigned int max_hz;
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void *regbase;
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void *ahbbase;
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bool is_decoded_cs;
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u32 fifo_depth;
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u32 fifo_width;
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u32 trigger_address;
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fdt_addr_t ahbsize;
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bool use_dac_mode;
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int read_delay;
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/* Flash parameters */
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u32 page_size;
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u32 block_size;
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u32 tshsl_ns;
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u32 tsd2d_ns;
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u32 tchsh_ns;
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u32 tslch_ns;
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bool is_dma;
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};
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struct cadence_spi_priv {
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unsigned int ref_clk_hz;
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unsigned int max_hz;
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void *regbase;
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void *ahbbase;
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unsigned int fifo_depth;
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unsigned int fifo_width;
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unsigned int trigger_address;
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fdt_addr_t ahbsize;
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size_t cmd_len;
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u8 cmd_buf[32];
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size_t data_len;
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int qspi_is_init;
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unsigned int qspi_calibrated_hz;
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unsigned int qspi_calibrated_cs;
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unsigned int previous_hz;
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u32 wr_delay;
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int read_delay;
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struct reset_ctl_bulk *resets;
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u32 page_size;
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u32 block_size;
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u32 tshsl_ns;
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u32 tsd2d_ns;
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u32 tchsh_ns;
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u32 tslch_ns;
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u8 edge_mode;
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u8 dll_mode;
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bool extra_dummy;
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bool ddr_init;
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bool is_decoded_cs;
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bool use_dac_mode;
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bool is_dma;
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/* Transaction protocol parameters. */
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u8 inst_width;
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u8 addr_width;
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u8 data_width;
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bool dtr;
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};
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/* Functions call declaration */
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void cadence_qspi_apb_controller_init(struct cadence_spi_priv *priv);
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void cadence_qspi_apb_controller_enable(void *reg_base_addr);
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void cadence_qspi_apb_controller_disable(void *reg_base_addr);
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void cadence_qspi_apb_dac_mode_enable(void *reg_base);
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int cadence_qspi_apb_command_read_setup(struct cadence_spi_priv *priv,
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const struct spi_mem_op *op);
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int cadence_qspi_apb_command_read(struct cadence_spi_priv *priv,
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const struct spi_mem_op *op);
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int cadence_qspi_apb_command_write_setup(struct cadence_spi_priv *priv,
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const struct spi_mem_op *op);
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int cadence_qspi_apb_command_write(struct cadence_spi_priv *priv,
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const struct spi_mem_op *op);
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int cadence_qspi_apb_read_setup(struct cadence_spi_priv *priv,
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const struct spi_mem_op *op);
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int cadence_qspi_apb_read_execute(struct cadence_spi_priv *priv,
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const struct spi_mem_op *op);
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int cadence_qspi_apb_write_setup(struct cadence_spi_priv *priv,
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const struct spi_mem_op *op);
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int cadence_qspi_apb_write_execute(struct cadence_spi_priv *priv,
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const struct spi_mem_op *op);
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void cadence_qspi_apb_chipselect(void *reg_base,
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unsigned int chip_select, unsigned int decoder_enable);
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void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
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void cadence_qspi_apb_config_baudrate_div(void *reg_base,
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unsigned int ref_clk_hz, unsigned int sclk_hz);
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void cadence_qspi_apb_delay(void *reg_base,
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unsigned int ref_clk, unsigned int sclk_hz,
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unsigned int tshsl_ns, unsigned int tsd2d_ns,
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unsigned int tchsh_ns, unsigned int tslch_ns);
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void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
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void cadence_qspi_apb_readdata_capture(void *reg_base,
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unsigned int bypass, unsigned int delay);
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unsigned int cm_get_qspi_controller_clk_hz(void);
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int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
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const struct spi_mem_op *op);
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int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv);
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int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg);
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int cadence_qspi_versal_flash_reset(struct udevice *dev);
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void cadence_qspi_apb_enable_linear_mode(bool enable);
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#endif /* __CADENCE_QSPI_H__ */
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