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https://github.com/AsahiLinux/u-boot
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d5f6a15a39
$ git grep CMD_DFL board/atc/ti113x.c:#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \ board/atc/ti113x.c: pci_writew (s, PCI_COMMAND, CMD_DFLT); board/cpc45/pd67290.c:#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \ board/cpc45/pd67290.c: pci_writew (s, PCI_COMMAND, CMD_DFLT); drivers/pcmcia/i82365.c:#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \ drivers/pcmcia/i82365.c: pci_writew (s, PCI_COMMAND, CMD_DFLT); include/configs/MBX.h:#define CONFIG_CMD_DFL include/configs/MigoR.h:#define CONFIG_CMD_DFL include/configs/digsy_mtc.h:#define CONFIG_CMD_DFL include/configs/ms7722se.h:#define CONFIG_CMD_DFL include/configs/ms7750se.h:#define CONFIG_CMD_DFL include/configs/r2dplus.h:#define CONFIG_CMD_DFL include/configs/sh7757lcr.h:#define CONFIG_CMD_DFL include/configs/sh7785lcr.h:#define CONFIG_CMD_DFL Signed-off-by: Marek Vasut <marex@denx.de> Cc: Pfister_Werner@intercontrol.de Cc: iwamatsu@nigauri.org Cc: nobuhiro.iwamatsu.yj@renesas.com Cc: vapier@gentoo.org Cc: wd@denx.de Cc: yoshihiro.shimoda.uh@renesas.com Acked-by: Anatolij Gustschin <agust@denx.de> Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
160 lines
4.7 KiB
C
160 lines
4.7 KiB
C
/*
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* Configuation settings for the sh7757lcr board
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*
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* Copyright (C) 2011 Renesas Solutions Corp.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __SH7757LCR_H
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#define __SH7757LCR_H
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#undef DEBUG
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#define CONFIG_SH 1
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#define CONFIG_SH4A 1
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#define CONFIG_SH_32BIT 1
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#define CONFIG_CPU_SH7757 1
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#define CONFIG_SH7757LCR 1
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#define CONFIG_SH7757LCR_DDR_ECC 1
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#define CONFIG_SYS_TEXT_BASE 0x8ef80000
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#define CONFIG_SYS_LDSCRIPT "board/renesas/sh7757lcr/u-boot.lds"
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_SF
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#define CONFIG_CMD_RUN
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#define CONFIG_CMD_SAVEENV
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#define CONFIG_CMD_MD5SUM
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#define CONFIG_MD5
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#define CONFIG_CMD_LOADS
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#define CONFIG_CMD_MMC
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#define CONFIG_CMD_EXT2
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#define CONFIG_DOS_PARTITION
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#define CONFIG_MAC_PARTITION
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp"
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#define CONFIG_VERSION_VARIABLE
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#undef CONFIG_SHOW_BOOT_PROGRESS
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/* MEMORY */
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#define SH7757LCR_SDRAM_BASE (0x80000000)
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#define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024)
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#define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */
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#define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024)
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_PROMPT "=> "
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_PBSIZE 256
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_BARGSIZE 512
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
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/* SCIF */
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#define CONFIG_SCIF_CONSOLE 1
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#define CONFIG_CONS_SCIF2 1
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#undef CONFIG_SYS_CONSOLE_INFO_QUIET
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#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
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#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
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#define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE)
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
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224 * 1024 * 1024)
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#undef CONFIG_SYS_ALT_MEMTEST
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#undef CONFIG_SYS_MEMTEST_SCRATCH
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#undef CONFIG_SYS_LOADS_BAUD_CHANGE
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#define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE)
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#define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE)
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
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(128 + 16) * 1024 * 1024)
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#define CONFIG_SYS_MONITOR_BASE 0x00000000
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
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#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
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/* FLASH */
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#define CONFIG_SYS_NO_FLASH
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/* Ether */
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#define CONFIG_SH_ETHER 1
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 1
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#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
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#define CONFIG_PHYLIB
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#define CONFIG_BITBANGMII
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#define CONFIG_BITBANGMII_MULTI
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#define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000
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#define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024)
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#define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI
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#define SH7757LCR_ETHERNET_MAC_SIZE 17
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#define SH7757LCR_ETHERNET_NUM_CH 2
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#define CONFIG_BOARD_LATE_INIT
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/* Gigabit Ether */
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#define SH7757LCR_GIGA_ETHERNET_NUM_CH 2
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/* SPI */
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#define CONFIG_SH_SPI 1
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#define CONFIG_SH_SPI_BASE 0xfe002000
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_STMICRO 1
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/* MMCIF */
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#define CONFIG_MMC 1
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#define CONFIG_GENERIC_MMC 1
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#define CONFIG_SH_MMCIF 1
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#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
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#define CONFIG_SH_MMCIF_CLK 48000000
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/* SH7757 board */
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#define SH7757LCR_SDRAM_PHYS_TOP 0x40000000
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#define SH7757LCR_GRA_OFFSET 0x1f000000
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#define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000
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#define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024)
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#define SH7757LCR_PCIEBRG_ADDR 0x00090000
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#define SH7757LCR_PCIEBRG_SIZE (96 * 1024)
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/* ENV setting */
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#define CONFIG_ENV_IS_EMBEDDED
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_SECT_SIZE (64 * 1024)
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#define CONFIG_ENV_ADDR (0x00080000)
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#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
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#define CONFIG_ENV_OVERWRITE 1
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#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netboot=bootp; bootm\0"
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 48000000
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#define CONFIG_SYS_HZ 1000
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#endif /* __SH7757LCR_H */
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