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https://github.com/AsahiLinux/u-boot
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ba94a1bba3
- Add IXP4xx NPE ethernet MAC support - Add support for Intel IXDPG425 board - Add support for Prodrive PDNB3 board - Add IRQ support Patch by Stefan Roese, 23 May 2006 [This patch does not include cpu/ixp/npe/IxNpeMicrocode.c which still sufferes from licensing issues. Blame Intel.]
796 lines
21 KiB
C
796 lines
21 KiB
C
/**
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* @file IxQMgrQAccess.c
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*
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* @author Intel Corporation
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* @date 30-Oct-2001
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*
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* @brief This file contains functions for putting entries on a queue and
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* removing entries from a queue.
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*
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*
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* @par
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* IXP400 SW Release version 2.0
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*
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* -- Copyright Notice --
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*
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* @par
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* Copyright 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* @par
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @par
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* -- End of Copyright Notice --
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*/
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/*
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* Inlines are compiled as function when this is defined.
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* N.B. Must be placed before #include of "IxQMgr.h"
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*/
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#ifndef IXQMGR_H
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# define IXQMGRQACCESS_C
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#else
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# error
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#endif
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/*
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* System defined include files.
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*/
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/*
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* User defined include files.
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*/
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#include "IxQMgr.h"
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#include "IxQMgrAqmIf_p.h"
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#include "IxQMgrQAccess_p.h"
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#include "IxQMgrQCfg_p.h"
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#include "IxQMgrDefines_p.h"
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/*
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* Global variables and extern definitions
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*/
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extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
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/*
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* Function definitions.
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*/
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void
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ixQMgrQAccessInit (void)
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{
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}
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IX_STATUS
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ixQMgrQReadWithChecks (IxQMgrQId qId,
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UINT32 *entry)
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{
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IxQMgrQEntrySizeInWords entrySizeInWords;
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IxQMgrQInlinedReadWriteInfo *infoPtr;
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if (NULL == entry)
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{
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return IX_QMGR_PARAMETER_ERROR;
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}
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/* Check QId */
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if (!ixQMgrQIsConfigured(qId))
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{
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return IX_QMGR_Q_NOT_CONFIGURED;
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}
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/* Get the q entry size in words */
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entrySizeInWords = ixQMgrQEntrySizeInWordsGet (qId);
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ixQMgrAqmIfQPop (qId, entrySizeInWords, entry);
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/* reset the current read count if the counter wrapped around
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* (unsigned arithmetic)
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*/
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infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
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if (infoPtr->qReadCount-- > infoPtr->qSizeInEntries)
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{
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infoPtr->qReadCount = 0;
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}
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/* Check if underflow occurred on the read */
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if (ixQMgrAqmIfUnderflowCheck (qId))
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{
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return IX_QMGR_Q_UNDERFLOW;
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}
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return IX_SUCCESS;
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}
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/* this function reads the remaining of the q entry
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* for queues configured with many words.
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* (the first word of the entry is already read
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* in the inlined function and the entry pointer already
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* incremented
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*/
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IX_STATUS
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ixQMgrQReadMWordsMinus1 (IxQMgrQId qId,
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UINT32 *entry)
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{
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IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
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UINT32 entrySize = infoPtr->qEntrySizeInWords;
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volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
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while (--entrySize)
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{
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/* read the entry and accumulate the result */
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*(++entry) = IX_OSAL_READ_LONG(++qAccRegAddr);
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}
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/* underflow is available for lower queues only */
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if (qId < IX_QMGR_MIN_QUEUPP_QID)
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{
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/* get the queue status */
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UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr);
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/* check the underflow status */
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if (status & infoPtr->qUflowStatBitMask)
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{
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/* the queue is empty
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* clear the underflow status bit if it was set
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*/
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IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr,
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status & ~infoPtr->qUflowStatBitMask);
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return IX_QMGR_Q_UNDERFLOW;
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}
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}
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return IX_SUCCESS;
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}
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IX_STATUS
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ixQMgrQWriteWithChecks (IxQMgrQId qId,
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UINT32 *entry)
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{
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IxQMgrQEntrySizeInWords entrySizeInWords;
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IxQMgrQInlinedReadWriteInfo *infoPtr;
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if (NULL == entry)
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{
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return IX_QMGR_PARAMETER_ERROR;
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}
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/* Check QId */
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if (!ixQMgrQIsConfigured(qId))
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{
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return IX_QMGR_Q_NOT_CONFIGURED;
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}
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/* Get the q entry size in words */
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entrySizeInWords = ixQMgrQEntrySizeInWordsGet (qId);
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ixQMgrAqmIfQPush (qId, entrySizeInWords, entry);
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/* reset the current read count if the counter wrapped around
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* (unsigned arithmetic)
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*/
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infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
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if (infoPtr->qWriteCount++ >= infoPtr->qSizeInEntries)
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{
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infoPtr->qWriteCount = infoPtr->qSizeInEntries;
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}
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/* Check if overflow occurred on the write*/
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if (ixQMgrAqmIfOverflowCheck (qId))
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{
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return IX_QMGR_Q_OVERFLOW;
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}
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return IX_SUCCESS;
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}
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IX_STATUS
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ixQMgrQPeek (IxQMgrQId qId,
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unsigned int entryIndex,
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UINT32 *entry)
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{
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unsigned int numEntries;
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#ifndef NDEBUG
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if ((NULL == entry) || (entryIndex >= IX_QMGR_Q_SIZE_INVALID))
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{
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return IX_QMGR_PARAMETER_ERROR;
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}
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if (!ixQMgrQIsConfigured(qId))
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{
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return IX_QMGR_Q_NOT_CONFIGURED;
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}
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#endif
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if (IX_SUCCESS != ixQMgrQNumEntriesGet (qId, &numEntries))
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{
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return IX_FAIL;
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}
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if (entryIndex >= numEntries) /* entryIndex starts at 0 */
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{
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return IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS;
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}
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return ixQMgrAqmIfQPeek (qId, entryIndex, entry);
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}
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IX_STATUS
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ixQMgrQPoke (IxQMgrQId qId,
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unsigned entryIndex,
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UINT32 *entry)
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{
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unsigned int numEntries;
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#ifndef NDEBUG
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if ((NULL == entry) || (entryIndex > 128))
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{
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return IX_QMGR_PARAMETER_ERROR;
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}
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if (!ixQMgrQIsConfigured(qId))
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{
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return IX_QMGR_Q_NOT_CONFIGURED;
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}
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#endif
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if (IX_SUCCESS != ixQMgrQNumEntriesGet (qId, &numEntries))
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{
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return IX_FAIL;
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}
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if (numEntries < (entryIndex + 1)) /* entryIndex starts at 0 */
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{
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return IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS;
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}
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return ixQMgrAqmIfQPoke (qId, entryIndex, entry);
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}
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IX_STATUS
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ixQMgrQStatusGetWithChecks (IxQMgrQId qId,
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IxQMgrQStatus *qStatus)
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{
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if (NULL == qStatus)
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{
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return IX_QMGR_PARAMETER_ERROR;
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}
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if (!ixQMgrQIsConfigured (qId))
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{
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return IX_QMGR_Q_NOT_CONFIGURED;
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}
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ixQMgrAqmIfQueStatRead (qId, qStatus);
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return IX_SUCCESS;
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}
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IX_STATUS
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ixQMgrQNumEntriesGet (IxQMgrQId qId,
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unsigned *numEntriesPtr)
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{
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UINT32 qPtrs;
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UINT32 qStatus;
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unsigned numEntries;
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IxQMgrQInlinedReadWriteInfo *infoPtr;
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#ifndef NDEBUG
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if (NULL == numEntriesPtr)
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{
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return IX_QMGR_PARAMETER_ERROR;
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}
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/* Check QId */
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if (!ixQMgrQIsConfigured(qId))
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{
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return IX_QMGR_Q_NOT_CONFIGURED;
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}
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#endif
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/* get fast access data */
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infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
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/* get snapshot */
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qPtrs = IX_OSAL_READ_LONG(infoPtr->qConfigRegAddr);
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/* Mod subtraction of pointers to get number of words in Q. */
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numEntries = (qPtrs - (qPtrs >> 7)) & 0x7f;
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if (numEntries == 0)
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{
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/*
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* Could mean either full or empty queue
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* so look at status
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*/
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ixQMgrAqmIfQueStatRead (qId, &qStatus);
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if (qId < IX_QMGR_MIN_QUEUPP_QID)
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{
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if (qStatus & IX_QMGR_Q_STATUS_E_BIT_MASK)
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{
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/* Empty */
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*numEntriesPtr = 0;
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}
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else if (qStatus & IX_QMGR_Q_STATUS_F_BIT_MASK)
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{
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/* Full */
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*numEntriesPtr = infoPtr->qSizeInEntries;
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}
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else
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{
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/*
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* Queue status and read/write pointers are volatile.
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* The queue state has changed since we took the
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* snapshot of the read and write pointers.
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* Client can retry if they wish
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*/
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*numEntriesPtr = 0;
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return IX_QMGR_WARNING;
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}
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}
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else /* It is an upper queue which does not have an empty status bit maintained */
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{
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if (qStatus & IX_QMGR_Q_STATUS_F_BIT_MASK)
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{
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/* The queue is Full at the time of snapshot. */
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*numEntriesPtr = infoPtr->qSizeInEntries;
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}
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else
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{
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/* The queue is either empty, either moving,
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* Client can retry if they wish
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*/
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*numEntriesPtr = 0;
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return IX_QMGR_WARNING;
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}
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}
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}
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else
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{
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*numEntriesPtr = (numEntries / infoPtr->qEntrySizeInWords) & (infoPtr->qSizeInEntries - 1);
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}
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return IX_SUCCESS;
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}
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#if defined(__wince) && defined(NO_INLINE_APIS)
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PUBLIC IX_STATUS
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ixQMgrQRead (IxQMgrQId qId,
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UINT32 *entryPtr)
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{
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extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
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IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
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UINT32 entry, entrySize;
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/* get a new entry */
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entrySize = infoPtr->qEntrySizeInWords;
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entry = IX_OSAL_READ_LONG(infoPtr->qAccRegAddr);
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if (entrySize != IX_QMGR_Q_ENTRY_SIZE1)
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{
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*entryPtr = entry;
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/* process the remaining part of the entry */
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return ixQMgrQReadMWordsMinus1(qId, entryPtr);
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}
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/* underflow is available for lower queues only */
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if (qId < IX_QMGR_MIN_QUEUPP_QID)
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{
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/* the counter of queue entries is decremented. In happy
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* day scenario there are many entries in the queue
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* and the counter does not reach zero.
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*/
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if (infoPtr->qReadCount-- == 0)
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{
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/* There is maybe no entry in the queue
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* qReadCount is now negative, but will be corrected before
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* the function returns.
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*/
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UINT32 qPtrs; /* queue internal pointers */
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/* when a queue is empty, the hw guarantees to return
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* a null value. If the value is not null, the queue is
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* not empty.
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*/
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if (entry == 0)
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{
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/* get the queue status */
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UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr);
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/* check the underflow status */
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if (status & infoPtr->qUflowStatBitMask)
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{
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/* the queue is empty
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* clear the underflow status bit if it was set
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*/
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IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr,
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status & ~infoPtr->qUflowStatBitMask);
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*entryPtr = 0;
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infoPtr->qReadCount = 0;
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return IX_QMGR_Q_UNDERFLOW;
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}
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}
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/* store the result */
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*entryPtr = entry;
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/* No underflow occured : someone is filling the queue
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* or the queue contains null entries.
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* The current counter needs to be
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* updated from the current number of entries in the queue
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*/
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/* get snapshot of queue pointers */
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qPtrs = IX_OSAL_READ_LONG(infoPtr->qConfigRegAddr);
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/* Mod subtraction of pointers to get number of words in Q. */
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qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f;
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if (qPtrs == 0)
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{
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/* no entry in the queue */
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infoPtr->qReadCount = 0;
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}
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else
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{
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/* convert the number of words inside the queue
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* to a number of entries
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*/
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infoPtr->qReadCount = qPtrs & (infoPtr->qSizeInEntries - 1);
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}
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return IX_SUCCESS;
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}
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}
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*entryPtr = entry;
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return IX_SUCCESS;
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}
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PUBLIC IX_STATUS
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ixQMgrQBurstRead (IxQMgrQId qId,
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UINT32 numEntries,
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UINT32 *entries)
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{
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extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
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IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
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UINT32 nullCheckEntry;
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if (infoPtr->qEntrySizeInWords == IX_QMGR_Q_ENTRY_SIZE1)
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{
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volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
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/* the code is optimized to take care of data dependencies:
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* Durig a read, there are a few cycles needed to get the
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* read complete. During these cycles, it is poossible to
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* do some CPU, e.g. increment pointers and decrement
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* counters.
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*/
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/* fetch a queue entry */
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nullCheckEntry = IX_OSAL_READ_LONG(infoPtr->qAccRegAddr);
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/* iterate the specified number of queue entries */
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while (--numEntries)
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{
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/* check the result of the previous read */
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if (nullCheckEntry == 0)
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{
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/* if we read a NULL entry, stop. We have underflowed */
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break;
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}
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else
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{
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/* write the entry */
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*entries = nullCheckEntry;
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/* fetch next entry */
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nullCheckEntry = IX_OSAL_READ_LONG(qAccRegAddr);
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/* increment the write address */
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entries++;
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}
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}
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/* write the pre-fetched entry */
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*entries = nullCheckEntry;
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}
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else
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{
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IxQMgrQEntrySizeInWords entrySizeInWords = infoPtr->qEntrySizeInWords;
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/* read the specified number of queue entries */
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nullCheckEntry = 0;
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while (numEntries--)
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{
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int i;
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for (i = 0; i < entrySizeInWords; i++)
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{
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*entries = IX_OSAL_READ_LONG(infoPtr->qAccRegAddr + i);
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nullCheckEntry |= *entries++;
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}
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/* if we read a NULL entry, stop. We have underflowed */
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if (nullCheckEntry == 0)
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{
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break;
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}
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nullCheckEntry = 0;
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}
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}
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/* reset the current read count : next access to the read function
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* will force a underflow status check
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*/
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infoPtr->qWriteCount = 0;
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/* Check if underflow occurred on the read */
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if (nullCheckEntry == 0 && qId < IX_QMGR_MIN_QUEUPP_QID)
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{
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/* get the queue status */
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UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr);
|
|
|
|
if (status & infoPtr->qUflowStatBitMask)
|
|
{
|
|
/* clear the underflow status bit if it was set */
|
|
IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr,
|
|
status & ~infoPtr->qUflowStatBitMask);
|
|
return IX_QMGR_Q_UNDERFLOW;
|
|
}
|
|
}
|
|
|
|
return IX_SUCCESS;
|
|
}
|
|
|
|
PUBLIC IX_STATUS
|
|
ixQMgrQWrite (IxQMgrQId qId,
|
|
UINT32 *entry)
|
|
{
|
|
extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
|
|
IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
|
|
UINT32 entrySize;
|
|
|
|
/* write the entry */
|
|
IX_OSAL_WRITE_LONG(infoPtr->qAccRegAddr, *entry);
|
|
entrySize = infoPtr->qEntrySizeInWords;
|
|
|
|
if (entrySize != IX_QMGR_Q_ENTRY_SIZE1)
|
|
{
|
|
/* process the remaining part of the entry */
|
|
volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
|
|
while (--entrySize)
|
|
{
|
|
++entry;
|
|
IX_OSAL_WRITE_LONG(++qAccRegAddr, *entry);
|
|
}
|
|
entrySize = infoPtr->qEntrySizeInWords;
|
|
}
|
|
|
|
/* overflow is available for lower queues only */
|
|
if (qId < IX_QMGR_MIN_QUEUPP_QID)
|
|
{
|
|
UINT32 qSize = infoPtr->qSizeInEntries;
|
|
/* increment the current number of entries in the queue
|
|
* and check for overflow
|
|
*/
|
|
if (infoPtr->qWriteCount++ == qSize)
|
|
{
|
|
/* the queue may have overflow */
|
|
UINT32 qPtrs; /* queue internal pointers */
|
|
|
|
/* get the queue status */
|
|
UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr);
|
|
|
|
/* read the status twice because the status may
|
|
* not be immediately ready after the write operation
|
|
*/
|
|
if ((status & infoPtr->qOflowStatBitMask) ||
|
|
((status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr))
|
|
& infoPtr->qOflowStatBitMask))
|
|
{
|
|
/* the queue is full, clear the overflow status
|
|
* bit if it was set
|
|
*/
|
|
IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr,
|
|
status & ~infoPtr->qOflowStatBitMask);
|
|
infoPtr->qWriteCount = infoPtr->qSizeInEntries;
|
|
return IX_QMGR_Q_OVERFLOW;
|
|
}
|
|
/* No overflow occured : someone is draining the queue
|
|
* and the current counter needs to be
|
|
* updated from the current number of entries in the queue
|
|
*/
|
|
|
|
/* get q pointer snapshot */
|
|
qPtrs = IX_OSAL_READ_LONG(infoPtr->qConfigRegAddr);
|
|
|
|
/* Mod subtraction of pointers to get number of words in Q. */
|
|
qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f;
|
|
|
|
if (qPtrs == 0)
|
|
{
|
|
/* the queue may be full at the time of the
|
|
* snapshot. Next access will check
|
|
* the overflow status again.
|
|
*/
|
|
infoPtr->qWriteCount = qSize;
|
|
}
|
|
else
|
|
{
|
|
/* convert the number of words to a number of entries */
|
|
if (entrySize == IX_QMGR_Q_ENTRY_SIZE1)
|
|
{
|
|
infoPtr->qWriteCount = qPtrs & (qSize - 1);
|
|
}
|
|
else
|
|
{
|
|
infoPtr->qWriteCount = (qPtrs / entrySize) & (qSize - 1);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return IX_SUCCESS;
|
|
}
|
|
|
|
PUBLIC IX_STATUS
|
|
ixQMgrQBurstWrite (IxQMgrQId qId,
|
|
unsigned numEntries,
|
|
UINT32 *entries)
|
|
{
|
|
extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
|
|
IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
|
|
UINT32 status;
|
|
|
|
/* update the current write count */
|
|
infoPtr->qWriteCount += numEntries;
|
|
|
|
if (infoPtr->qEntrySizeInWords == IX_QMGR_Q_ENTRY_SIZE1)
|
|
{
|
|
volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr;
|
|
while (numEntries--)
|
|
{
|
|
IX_OSAL_WRITE_LONG(qAccRegAddr, *entries);
|
|
entries++;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
IxQMgrQEntrySizeInWords entrySizeInWords = infoPtr->qEntrySizeInWords;
|
|
int i;
|
|
|
|
/* write each queue entry */
|
|
while (numEntries--)
|
|
{
|
|
/* write the queueEntrySize number of words for each entry */
|
|
for (i = 0; i < entrySizeInWords; i++)
|
|
{
|
|
IX_OSAL_WRITE_LONG((infoPtr->qAccRegAddr + i), *entries);
|
|
entries++;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* check if the write count overflows */
|
|
if (infoPtr->qWriteCount > infoPtr->qSizeInEntries)
|
|
{
|
|
/* reset the current write count */
|
|
infoPtr->qWriteCount = infoPtr->qSizeInEntries;
|
|
}
|
|
|
|
/* Check if overflow occurred on the write operation */
|
|
if (qId < IX_QMGR_MIN_QUEUPP_QID)
|
|
{
|
|
/* get the queue status */
|
|
status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr);
|
|
|
|
/* read the status twice because the status may
|
|
* not be ready at the time of the write
|
|
*/
|
|
if ((status & infoPtr->qOflowStatBitMask) ||
|
|
((status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr))
|
|
& infoPtr->qOflowStatBitMask))
|
|
{
|
|
/* clear the underflow status bit if it was set */
|
|
IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr,
|
|
status & ~infoPtr->qOflowStatBitMask);
|
|
return IX_QMGR_Q_OVERFLOW;
|
|
}
|
|
}
|
|
|
|
return IX_SUCCESS;
|
|
}
|
|
|
|
PUBLIC IX_STATUS
|
|
ixQMgrQStatusGet (IxQMgrQId qId,
|
|
IxQMgrQStatus *qStatus)
|
|
{
|
|
/* read the status of a queue in the range 0-31 */
|
|
if (qId < IX_QMGR_MIN_QUEUPP_QID)
|
|
{
|
|
extern UINT32 ixQMgrAqmIfQueLowStatRegAddr[];
|
|
extern UINT32 ixQMgrAqmIfQueLowStatBitsOffset[];
|
|
extern UINT32 ixQMgrAqmIfQueLowStatBitsMask;
|
|
extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[];
|
|
IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId];
|
|
volatile UINT32 *lowStatRegAddr = (UINT32*)ixQMgrAqmIfQueLowStatRegAddr[qId];
|
|
volatile UINT32 *qUOStatRegAddr = infoPtr->qUOStatRegAddr;
|
|
|
|
UINT32 lowStatBitsOffset = ixQMgrAqmIfQueLowStatBitsOffset[qId];
|
|
UINT32 lowStatBitsMask = ixQMgrAqmIfQueLowStatBitsMask;
|
|
UINT32 underflowBitMask = infoPtr->qUflowStatBitMask;
|
|
UINT32 overflowBitMask = infoPtr->qOflowStatBitMask;
|
|
|
|
/* read the status register for this queue */
|
|
*qStatus = IX_OSAL_READ_LONG(lowStatRegAddr);
|
|
/* mask out the status bits relevant only to this queue */
|
|
*qStatus = (*qStatus >> lowStatBitsOffset) & lowStatBitsMask;
|
|
|
|
/* Check if the queue has overflowed */
|
|
if (IX_OSAL_READ_LONG(qUOStatRegAddr) & overflowBitMask)
|
|
{
|
|
/* clear the overflow status bit if it was set */
|
|
IX_OSAL_WRITE_LONG(qUOStatRegAddr,
|
|
(IX_OSAL_READ_LONG(qUOStatRegAddr) &
|
|
~overflowBitMask));
|
|
*qStatus |= IX_QMGR_Q_STATUS_OF_BIT_MASK;
|
|
}
|
|
|
|
/* Check if the queue has underflowed */
|
|
if (IX_OSAL_READ_LONG(qUOStatRegAddr) & underflowBitMask)
|
|
{
|
|
/* clear the underflow status bit if it was set */
|
|
IX_OSAL_WRITE_LONG(qUOStatRegAddr,
|
|
(IX_OSAL_READ_LONG(qUOStatRegAddr) &
|
|
~underflowBitMask));
|
|
*qStatus |= IX_QMGR_Q_STATUS_UF_BIT_MASK;
|
|
}
|
|
}
|
|
else /* read status of a queue in the range 32-63 */
|
|
{
|
|
extern UINT32 ixQMgrAqmIfQueUppStat0RegAddr;
|
|
extern UINT32 ixQMgrAqmIfQueUppStat1RegAddr;
|
|
extern UINT32 ixQMgrAqmIfQueUppStat0BitMask[];
|
|
extern UINT32 ixQMgrAqmIfQueUppStat1BitMask[];
|
|
|
|
volatile UINT32 *qNearEmptyStatRegAddr = (UINT32*)ixQMgrAqmIfQueUppStat0RegAddr;
|
|
volatile UINT32 *qFullStatRegAddr = (UINT32*)ixQMgrAqmIfQueUppStat1RegAddr;
|
|
int maskIndex = qId - IX_QMGR_MIN_QUEUPP_QID;
|
|
UINT32 qNearEmptyStatBitMask = ixQMgrAqmIfQueUppStat0BitMask[maskIndex];
|
|
UINT32 qFullStatBitMask = ixQMgrAqmIfQueUppStat1BitMask[maskIndex];
|
|
|
|
/* Reset the status bits */
|
|
*qStatus = 0;
|
|
|
|
/* Check if the queue is nearly empty */
|
|
if (IX_OSAL_READ_LONG(qNearEmptyStatRegAddr) & qNearEmptyStatBitMask)
|
|
{
|
|
*qStatus |= IX_QMGR_Q_STATUS_NE_BIT_MASK;
|
|
}
|
|
|
|
/* Check if the queue is full */
|
|
if (IX_OSAL_READ_LONG(qFullStatRegAddr) & qFullStatBitMask)
|
|
{
|
|
*qStatus |= IX_QMGR_Q_STATUS_F_BIT_MASK;
|
|
}
|
|
}
|
|
return IX_SUCCESS;
|
|
}
|
|
#endif /* def NO_INLINE_APIS */
|