mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 22:03:15 +00:00
3d3fdaf075
In order to use the TCB early in boot and in the SPL, add u-boot,dm-pre-reloc property for the TCB and the clock that is used by the driver (tcb0_clk). Signed-off-by: Clément Léger <clement.leger@bootlin.com>
822 lines
17 KiB
Text
822 lines
17 KiB
Text
#include "skeleton.dtsi"
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
|
|
/ {
|
|
model = "Atmel SAMA5D2 family SoC";
|
|
compatible = "atmel,sama5d2";
|
|
interrupt-parent = <&aic>;
|
|
|
|
aliases {
|
|
spi0 = &spi0;
|
|
spi1 = &qspi0;
|
|
spi2 = &qspi1;
|
|
i2c0 = &i2c0;
|
|
i2c1 = &i2c1;
|
|
};
|
|
|
|
clocks {
|
|
slow_xtal: slow_xtal {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
main_xtal: main_xtal {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <0>;
|
|
};
|
|
};
|
|
|
|
ahb {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
u-boot,dm-pre-reloc;
|
|
|
|
usb1: ohci@400000 {
|
|
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
|
|
reg = <0x00400000 0x100000>;
|
|
clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
|
|
clock-names = "ohci_clk", "hclk", "uhpck";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb2: ehci@500000 {
|
|
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
|
|
reg = <0x00500000 0x100000>;
|
|
clocks = <&utmi>, <&uhphs_clk>;
|
|
clock-names = "usb_clk", "ehci_clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
sdmmc0: sdio-host@a0000000 {
|
|
compatible = "atmel,sama5d2-sdhci";
|
|
reg = <0xa0000000 0x300>;
|
|
clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
|
|
clock-names = "hclock", "multclk", "baseclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
sdmmc1: sdio-host@b0000000 {
|
|
compatible = "atmel,sama5d2-sdhci";
|
|
reg = <0xb0000000 0x300>;
|
|
clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
|
|
clock-names = "hclock", "multclk", "baseclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
apb {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
u-boot,dm-pre-reloc;
|
|
|
|
hlcdc: hlcdc@f0000000 {
|
|
compatible = "atmel,at91sam9x5-hlcdc";
|
|
reg = <0xf0000000 0x2000>;
|
|
clocks = <&lcdc_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pmc: pmc@f0014000 {
|
|
compatible = "atmel,sama5d2-pmc", "syscon";
|
|
reg = <0xf0014000 0x160>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
u-boot,dm-pre-reloc;
|
|
|
|
main: mainck {
|
|
compatible = "atmel,at91sam9x5-clk-main";
|
|
#clock-cells = <0>;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
plla: pllack@0 {
|
|
compatible = "atmel,sama5d3-clk-pll";
|
|
#clock-cells = <0>;
|
|
clocks = <&main>;
|
|
reg = <0>;
|
|
atmel,clk-input-range = <12000000 12000000>;
|
|
#atmel,pll-clk-output-range-cells = <4>;
|
|
atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
plladiv: plladivck {
|
|
compatible = "atmel,at91sam9x5-clk-plldiv";
|
|
#clock-cells = <0>;
|
|
clocks = <&plla>;
|
|
};
|
|
|
|
audio_pll_frac: audiopll_fracck {
|
|
compatible = "atmel,sama5d2-clk-audio-pll-frac";
|
|
#clock-cells = <0>;
|
|
clocks = <&main>;
|
|
};
|
|
|
|
audio_pll_pad: audiopll_padck {
|
|
compatible = "atmel,sama5d2-clk-audio-pll-pad";
|
|
#clock-cells = <0>;
|
|
clocks = <&audio_pll_frac>;
|
|
};
|
|
|
|
audio_pll_pmc: audiopll_pmcck {
|
|
compatible = "atmel,sama5d2-clk-audio-pll-pmc";
|
|
#clock-cells = <0>;
|
|
clocks = <&audio_pll_frac>;
|
|
};
|
|
|
|
utmi: utmick {
|
|
compatible = "atmel,at91sam9x5-clk-utmi";
|
|
#clock-cells = <0>;
|
|
clocks = <&main>;
|
|
regmap-sfr = <&sfr>;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
mck: masterck {
|
|
compatible = "atmel,at91sam9x5-clk-master";
|
|
#clock-cells = <0>;
|
|
clocks = <&main>, <&plladiv>, <&utmi>;
|
|
atmel,clk-output-range = <124000000 166000000>;
|
|
atmel,clk-divisors = <1 2 4 3>;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
h32ck: h32mxck {
|
|
#clock-cells = <0>;
|
|
compatible = "atmel,sama5d4-clk-h32mx";
|
|
clocks = <&mck>;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
usb: usbck {
|
|
compatible = "atmel,at91sam9x5-clk-usb";
|
|
#clock-cells = <0>;
|
|
clocks = <&plladiv>, <&utmi>;
|
|
};
|
|
|
|
prog: progck {
|
|
compatible = "atmel,at91sam9x5-clk-programmable";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupt-parent = <&pmc>;
|
|
clocks = <&main>, <&plladiv>, <&utmi>, <&mck>;
|
|
|
|
prog0: prog@0 {
|
|
#clock-cells = <0>;
|
|
reg = <0>;
|
|
};
|
|
|
|
prog1: prog@1 {
|
|
#clock-cells = <0>;
|
|
reg = <1>;
|
|
};
|
|
|
|
prog2: prog@2 {
|
|
#clock-cells = <0>;
|
|
reg = <2>;
|
|
};
|
|
};
|
|
|
|
systemck {
|
|
compatible = "atmel,at91rm9200-clk-system";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
ddrck: ddrck@2 {
|
|
#clock-cells = <0>;
|
|
reg = <2>;
|
|
clocks = <&mck>;
|
|
};
|
|
|
|
lcdck: lcdck@3 {
|
|
#clock-cells = <0>;
|
|
reg = <3>;
|
|
clocks = <&mck>;
|
|
};
|
|
|
|
uhpck: uhpck@6 {
|
|
#clock-cells = <0>;
|
|
reg = <6>;
|
|
clocks = <&usb>;
|
|
};
|
|
|
|
udpck: udpck@7 {
|
|
#clock-cells = <0>;
|
|
reg = <7>;
|
|
clocks = <&usb>;
|
|
};
|
|
|
|
pck0: pck0@8 {
|
|
#clock-cells = <0>;
|
|
reg = <8>;
|
|
clocks = <&prog0>;
|
|
};
|
|
|
|
pck1: pck1@9 {
|
|
#clock-cells = <0>;
|
|
reg = <9>;
|
|
clocks = <&prog1>;
|
|
};
|
|
|
|
pck2: pck2@10 {
|
|
#clock-cells = <0>;
|
|
reg = <10>;
|
|
clocks = <&prog2>;
|
|
};
|
|
|
|
iscck: iscck@18 {
|
|
#clock-cells = <0>;
|
|
reg = <18>;
|
|
clocks = <&mck>;
|
|
};
|
|
};
|
|
|
|
periph32ck {
|
|
compatible = "atmel,at91sam9x5-clk-peripheral";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&h32ck>;
|
|
u-boot,dm-pre-reloc;
|
|
|
|
macb0_clk: macb0_clk@5 {
|
|
#clock-cells = <0>;
|
|
reg = <5>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
tdes_clk: tdes_clk@11 {
|
|
#clock-cells = <0>;
|
|
reg = <11>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
matrix1_clk: matrix1_clk@14 {
|
|
#clock-cells = <0>;
|
|
reg = <14>;
|
|
};
|
|
|
|
hsmc_clk: hsmc_clk@17 {
|
|
#clock-cells = <0>;
|
|
reg = <17>;
|
|
};
|
|
|
|
pioA_clk: pioA_clk@18 {
|
|
#clock-cells = <0>;
|
|
reg = <18>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
flx0_clk: flx0_clk@19 {
|
|
#clock-cells = <0>;
|
|
reg = <19>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
flx1_clk: flx1_clk@20 {
|
|
#clock-cells = <0>;
|
|
reg = <20>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
flx2_clk: flx2_clk@21 {
|
|
#clock-cells = <0>;
|
|
reg = <21>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
flx3_clk: flx3_clk@22 {
|
|
#clock-cells = <0>;
|
|
reg = <22>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
flx4_clk: flx4_clk@23 {
|
|
#clock-cells = <0>;
|
|
reg = <23>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
uart0_clk: uart0_clk@24 {
|
|
#clock-cells = <0>;
|
|
reg = <24>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
uart1_clk: uart1_clk@25 {
|
|
#clock-cells = <0>;
|
|
reg = <25>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
uart2_clk: uart2_clk@26 {
|
|
#clock-cells = <0>;
|
|
reg = <26>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
uart3_clk: uart3_clk@27 {
|
|
#clock-cells = <0>;
|
|
reg = <27>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
uart4_clk: uart4_clk@28 {
|
|
#clock-cells = <0>;
|
|
reg = <28>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
twi0_clk: twi0_clk@29 {
|
|
reg = <29>;
|
|
#clock-cells = <0>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
twi1_clk: twi1_clk@30 {
|
|
#clock-cells = <0>;
|
|
reg = <30>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
spi0_clk: spi0_clk@33 {
|
|
#clock-cells = <0>;
|
|
reg = <33>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
spi1_clk: spi1_clk@34 {
|
|
#clock-cells = <0>;
|
|
reg = <34>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
tcb0_clk: tcb0_clk@35 {
|
|
#clock-cells = <0>;
|
|
reg = <35>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
tcb1_clk: tcb1_clk@36 {
|
|
#clock-cells = <0>;
|
|
reg = <36>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
pwm_clk: pwm_clk@38 {
|
|
#clock-cells = <0>;
|
|
reg = <38>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
adc_clk: adc_clk@40 {
|
|
#clock-cells = <0>;
|
|
reg = <40>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
uhphs_clk: uhphs_clk@41 {
|
|
#clock-cells = <0>;
|
|
reg = <41>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
udphs_clk: udphs_clk@42 {
|
|
#clock-cells = <0>;
|
|
reg = <42>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
ssc0_clk: ssc0_clk@43 {
|
|
#clock-cells = <0>;
|
|
reg = <43>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
ssc1_clk: ssc1_clk@44 {
|
|
#clock-cells = <0>;
|
|
reg = <44>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
trng_clk: trng_clk@47 {
|
|
#clock-cells = <0>;
|
|
reg = <47>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
pdmic_clk: pdmic_clk@48 {
|
|
#clock-cells = <0>;
|
|
reg = <48>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
i2s0_clk: i2s0_clk@54 {
|
|
#clock-cells = <0>;
|
|
reg = <54>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
i2s1_clk: i2s1_clk@55 {
|
|
#clock-cells = <0>;
|
|
reg = <55>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
can0_clk: can0_clk@56 {
|
|
#clock-cells = <0>;
|
|
reg = <56>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
can1_clk: can1_clk@57 {
|
|
#clock-cells = <0>;
|
|
reg = <57>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
classd_clk: classd_clk@59 {
|
|
#clock-cells = <0>;
|
|
reg = <59>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
};
|
|
|
|
periph64ck {
|
|
compatible = "atmel,at91sam9x5-clk-peripheral";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&mck>;
|
|
u-boot,dm-pre-reloc;
|
|
|
|
dma0_clk: dma0_clk@6 {
|
|
#clock-cells = <0>;
|
|
reg = <6>;
|
|
};
|
|
|
|
dma1_clk: dma1_clk@7 {
|
|
#clock-cells = <0>;
|
|
reg = <7>;
|
|
};
|
|
|
|
aes_clk: aes_clk@9 {
|
|
#clock-cells = <0>;
|
|
reg = <9>;
|
|
};
|
|
|
|
aesb_clk: aesb_clk@10 {
|
|
#clock-cells = <0>;
|
|
reg = <10>;
|
|
};
|
|
|
|
sha_clk: sha_clk@12 {
|
|
#clock-cells = <0>;
|
|
reg = <12>;
|
|
};
|
|
|
|
mpddr_clk: mpddr_clk@13 {
|
|
#clock-cells = <0>;
|
|
reg = <13>;
|
|
};
|
|
|
|
matrix0_clk: matrix0_clk@15 {
|
|
#clock-cells = <0>;
|
|
reg = <15>;
|
|
};
|
|
|
|
sdmmc0_hclk: sdmmc0_hclk@31 {
|
|
#clock-cells = <0>;
|
|
reg = <31>;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
sdmmc1_hclk: sdmmc1_hclk@32 {
|
|
#clock-cells = <0>;
|
|
reg = <32>;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
lcdc_clk: lcdc_clk@45 {
|
|
#clock-cells = <0>;
|
|
reg = <45>;
|
|
};
|
|
|
|
isc_clk: isc_clk@46 {
|
|
#clock-cells = <0>;
|
|
reg = <46>;
|
|
};
|
|
|
|
qspi0_clk: qspi0_clk@52 {
|
|
#clock-cells = <0>;
|
|
reg = <52>;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
qspi1_clk: qspi1_clk@53 {
|
|
#clock-cells = <0>;
|
|
reg = <53>;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
};
|
|
|
|
gck {
|
|
compatible = "atmel,sama5d2-clk-generated";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupt-parent = <&pmc>;
|
|
clocks = <&main>, <&plla>, <&utmi>, <&mck>;
|
|
u-boot,dm-pre-reloc;
|
|
|
|
sdmmc0_gclk: sdmmc0_gclk@31 {
|
|
#clock-cells = <0>;
|
|
reg = <31>;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
sdmmc1_gclk: sdmmc1_gclk@32 {
|
|
#clock-cells = <0>;
|
|
reg = <32>;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
tcb0_gclk: tcb0_gclk@35 {
|
|
#clock-cells = <0>;
|
|
reg = <35>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
tcb1_gclk: tcb1_gclk@36 {
|
|
#clock-cells = <0>;
|
|
reg = <36>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
pwm_gclk: pwm_gclk@38 {
|
|
#clock-cells = <0>;
|
|
reg = <38>;
|
|
atmel,clk-output-range = <0 83000000>;
|
|
};
|
|
|
|
pdmic_gclk: pdmic_gclk@48 {
|
|
#clock-cells = <0>;
|
|
reg = <48>;
|
|
};
|
|
|
|
i2s0_gclk: i2s0_gclk@54 {
|
|
#clock-cells = <0>;
|
|
reg = <54>;
|
|
};
|
|
|
|
i2s1_gclk: i2s1_gclk@55 {
|
|
#clock-cells = <0>;
|
|
reg = <55>;
|
|
};
|
|
|
|
can0_gclk: can0_gclk@56 {
|
|
#clock-cells = <0>;
|
|
reg = <56>;
|
|
atmel,clk-output-range = <0 80000000>;
|
|
};
|
|
|
|
can1_gclk: can1_gclk@57 {
|
|
#clock-cells = <0>;
|
|
reg = <57>;
|
|
atmel,clk-output-range = <0 80000000>;
|
|
};
|
|
|
|
classd_gclk: classd_gclk@59 {
|
|
#clock-cells = <0>;
|
|
reg = <59>;
|
|
atmel,clk-output-range = <0 100000000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qspi0: spi@f0020000 {
|
|
compatible = "atmel,sama5d2-qspi";
|
|
reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
|
|
reg-names = "qspi_base", "qspi_mmap";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&qspi0_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qspi1: spi@f0024000 {
|
|
compatible = "atmel,sama5d2-qspi";
|
|
reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
|
|
reg-names = "qspi_base", "qspi_mmap";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&qspi1_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@f8000000 {
|
|
compatible = "atmel,at91rm9200-spi";
|
|
reg = <0xf8000000 0x100>;
|
|
clocks = <&spi0_clk>;
|
|
clock-names = "spi_clk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
macb0: ethernet@f8008000 {
|
|
compatible = "cdns,macb";
|
|
reg = <0xf8008000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&macb0_clk>, <&macb0_clk>;
|
|
clock-names = "hclk", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
tcb0: timer@f800c000 {
|
|
compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
|
|
reg = <0xf800c000 0x100>;
|
|
interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
clocks = <&tcb0_clk>, <&tcb0_gclk>, <&clk32k>;
|
|
clock-names = "t0_clk", "gclk", "slow_clk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
u-boot,dm-pre-reloc;
|
|
|
|
timer0: timer@0 {
|
|
compatible = "atmel,tcb-timer";
|
|
reg = <0>, <1>;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
};
|
|
|
|
uart0: serial@f801c000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf801c000 0x100>;
|
|
clocks = <&uart0_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@f8020000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf8020000 0x100>;
|
|
clocks = <&uart1_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@f8024000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xf8024000 0x100>;
|
|
clocks = <&uart2_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@f8028000 {
|
|
compatible = "atmel,sama5d2-i2c";
|
|
reg = <0xf8028000 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&twi0_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm0: pwm@f802c000 {
|
|
compatible = "atmel,sama5d2-pwm";
|
|
reg = <0xf802c000 0x4000>;
|
|
clocks = <&pwm_clk>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rstc@f8048000 {
|
|
compatible = "atmel,sama5d3-rstc";
|
|
reg = <0xf8048000 0x10>;
|
|
clocks = <&clk32k>;
|
|
};
|
|
|
|
shdwc@f8048010 {
|
|
compatible = "atmel,sama5d2-shdwc";
|
|
reg = <0xf8048010 0x10>;
|
|
clocks = <&clk32k>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
atmel,wakeup-rtc-timer;
|
|
};
|
|
|
|
pit: timer@f8048030 {
|
|
compatible = "atmel,at91sam9260-pit";
|
|
reg = <0xf8048030 0x10>;
|
|
clocks = <&h32ck>;
|
|
};
|
|
|
|
watchdog@f8048040 {
|
|
compatible = "atmel,sama5d4-wdt";
|
|
reg = <0xf8048040 0x10>;
|
|
clocks = <&clk32k>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sfr: sfr@f8030000 {
|
|
compatible = "atmel,sama5d2-sfr", "syscon";
|
|
reg = <0xf8030000 0x98>;
|
|
};
|
|
|
|
sckc@f8048050 {
|
|
compatible = "atmel,at91sam9x5-sckc";
|
|
reg = <0xf8048050 0x4>;
|
|
|
|
slow_rc_osc: slow_rc_osc {
|
|
compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32768>;
|
|
clock-accuracy = <250000000>;
|
|
atmel,startup-time-usec = <75>;
|
|
};
|
|
|
|
slow_osc: slow_osc {
|
|
compatible = "atmel,at91sam9x5-clk-slow-osc";
|
|
#clock-cells = <0>;
|
|
clocks = <&slow_xtal>;
|
|
atmel,startup-time-usec = <1200000>;
|
|
};
|
|
|
|
clk32k: slowck {
|
|
compatible = "atmel,at91sam9x5-clk-slow";
|
|
#clock-cells = <0>;
|
|
clocks = <&slow_rc_osc &slow_osc>;
|
|
};
|
|
};
|
|
|
|
spi1: spi@fc000000 {
|
|
compatible = "atmel,at91rm9200-spi";
|
|
reg = <0xfc000000 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@fc008000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xfc008000 0x100>;
|
|
clocks = <&uart3_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@fc00c000 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0xfc00c000 0x100>;
|
|
clocks = <&uart4_clk>;
|
|
clock-names = "usart";
|
|
status = "disabled";
|
|
};
|
|
|
|
aic: interrupt-controller@fc020000 {
|
|
#interrupt-cells = <3>;
|
|
compatible = "atmel,sama5d2-aic";
|
|
interrupt-controller;
|
|
reg = <0xfc020000 0x200>;
|
|
atmel,external-irqs = <49>;
|
|
};
|
|
|
|
i2c1: i2c@fc028000 {
|
|
compatible = "atmel,sama5d2-i2c";
|
|
reg = <0xfc028000 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&twi1_clk>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pioA: gpio@fc038000 {
|
|
compatible = "atmel,sama5d2-gpio";
|
|
reg = <0xfc038000 0x600>;
|
|
clocks = <&pioA_clk>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
u-boot,dm-pre-reloc;
|
|
|
|
pinctrl {
|
|
compatible = "atmel,sama5d2-pinctrl";
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
onewire_tm: onewire {
|
|
compatible = "w1-gpio";
|
|
status = "disabled";
|
|
};
|
|
};
|