mirror of
https://github.com/AsahiLinux/u-boot
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4194b3668a
Add a disable sub-command to the cpu command that allows for disabling cores in multicore processors. This can be useful for systems that are using multicore chips but aren't utilizing all the cores as a way to reduce power and possibly improve performance. Also updated an added missing copyright. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
111 lines
2.9 KiB
C
111 lines
2.9 KiB
C
/*
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* Copyright 2008-2010 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <ioports.h>
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#include <lmb.h>
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#include <asm/io.h>
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#include <asm/mp.h>
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DECLARE_GLOBAL_DATA_PTR;
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int cpu_reset(int nr)
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{
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/* dummy function so common/cmd_mp.c will build
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* should be implemented in the future, when cpu_release()
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* is supported. Be aware there may be a similiar bug
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* as exists on MPC85xx w/its PIC having a timing window
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* associated to resetting the core */
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return 1;
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}
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int cpu_status(int nr)
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{
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/* dummy function so common/cmd_mp.c will build */
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return 0;
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}
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int cpu_disable(int nr)
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{
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/* dummy function so common/cmd_mp.c will build */
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return 1;
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}
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int cpu_release(int nr, int argc, char *argv[])
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{
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/* dummy function so common/cmd_mp.c will build
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* should be implemented in the future */
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return 1;
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}
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u32 determine_mp_bootpg(void)
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{
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/* if we have 4G or more of memory, put the boot page at 4Gb-1M */
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if ((u64)gd->ram_size > 0xfffff000)
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return (0xfff00000);
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return (gd->ram_size - (1024 * 1024));
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}
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void cpu_mp_lmb_reserve(struct lmb *lmb)
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{
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u32 bootpg = determine_mp_bootpg();
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/* tell u-boot we stole a page */
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lmb_reserve(lmb, bootpg, 4096);
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}
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/*
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* Copy the code for other cpus to execute into an
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* aligned location accessible via BPTR
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*/
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void setup_mp(void)
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{
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extern ulong __secondary_start_page;
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ulong fixup = (ulong)&__secondary_start_page;
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u32 bootpg = determine_mp_bootpg();
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u32 bootpg_va;
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if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) {
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/* We're not covered by the DDR mapping, set up BAT */
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write_bat(DBAT7, CONFIG_SYS_SCRATCH_VA | BATU_BL_128K |
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BATU_VS | BATU_VP,
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bootpg | BATL_PP_RW | BATL_MEMCOHERENCE);
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bootpg_va = CONFIG_SYS_SCRATCH_VA;
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} else {
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bootpg_va = bootpg;
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}
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memcpy((void *)bootpg_va, (void *)fixup, 4096);
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flush_cache(bootpg_va, 4096);
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/* remove the temporary BAT mapping */
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if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE)
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write_bat(DBAT7, 0, 0);
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/* If the physical location of bootpg is not at fff00000, set BPTR */
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if (bootpg != 0xfff00000)
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out_be32((uint *)(CONFIG_SYS_CCSRBAR + 0x20), 0x80000000 |
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(bootpg >> 12));
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}
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