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c61897bf02
Currently, the I2C clocks are configured in the sunxi board code. Add the I2C clocks to the DM clock driver so they can be enabled from the DM I2C driver using the normal uclass methods. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
111 lines
3.1 KiB
C
111 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Amarula Solutions.
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <clk/sunxi.h>
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#include <dt-bindings/clock/sun9i-a80-ccu.h>
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#include <dt-bindings/reset/sun9i-a80-ccu.h>
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#include <linux/bitops.h>
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static const struct ccu_clk_gate a80_gates[] = {
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[CLK_SPI0] = GATE(0x430, BIT(31)),
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[CLK_SPI1] = GATE(0x434, BIT(31)),
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[CLK_SPI2] = GATE(0x438, BIT(31)),
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[CLK_SPI3] = GATE(0x43c, BIT(31)),
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[CLK_BUS_MMC] = GATE(0x580, BIT(8)),
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[CLK_BUS_SPI0] = GATE(0x580, BIT(20)),
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[CLK_BUS_SPI1] = GATE(0x580, BIT(21)),
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[CLK_BUS_SPI2] = GATE(0x580, BIT(22)),
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[CLK_BUS_SPI3] = GATE(0x580, BIT(23)),
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[CLK_BUS_I2C0] = GATE(0x594, BIT(0)),
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[CLK_BUS_I2C1] = GATE(0x594, BIT(1)),
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[CLK_BUS_I2C2] = GATE(0x594, BIT(2)),
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[CLK_BUS_I2C3] = GATE(0x594, BIT(3)),
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[CLK_BUS_I2C4] = GATE(0x594, BIT(4)),
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[CLK_BUS_UART0] = GATE(0x594, BIT(16)),
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[CLK_BUS_UART1] = GATE(0x594, BIT(17)),
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[CLK_BUS_UART2] = GATE(0x594, BIT(18)),
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[CLK_BUS_UART3] = GATE(0x594, BIT(19)),
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[CLK_BUS_UART4] = GATE(0x594, BIT(20)),
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[CLK_BUS_UART5] = GATE(0x594, BIT(21)),
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};
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static const struct ccu_reset a80_resets[] = {
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[RST_BUS_MMC] = RESET(0x5a0, BIT(8)),
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[RST_BUS_SPI0] = RESET(0x5a0, BIT(20)),
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[RST_BUS_SPI1] = RESET(0x5a0, BIT(21)),
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[RST_BUS_SPI2] = RESET(0x5a0, BIT(22)),
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[RST_BUS_SPI3] = RESET(0x5a0, BIT(23)),
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[RST_BUS_I2C0] = RESET(0x5b4, BIT(0)),
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[RST_BUS_I2C1] = RESET(0x5b4, BIT(1)),
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[RST_BUS_I2C2] = RESET(0x5b4, BIT(2)),
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[RST_BUS_I2C3] = RESET(0x5b4, BIT(3)),
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[RST_BUS_I2C4] = RESET(0x5b4, BIT(4)),
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[RST_BUS_UART0] = RESET(0x5b4, BIT(16)),
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[RST_BUS_UART1] = RESET(0x5b4, BIT(17)),
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[RST_BUS_UART2] = RESET(0x5b4, BIT(18)),
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[RST_BUS_UART3] = RESET(0x5b4, BIT(19)),
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[RST_BUS_UART4] = RESET(0x5b4, BIT(20)),
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[RST_BUS_UART5] = RESET(0x5b4, BIT(21)),
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};
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static const struct ccu_clk_gate a80_mmc_gates[] = {
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[0] = GATE(0x0, BIT(16)),
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[1] = GATE(0x4, BIT(16)),
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[2] = GATE(0x8, BIT(16)),
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[3] = GATE(0xc, BIT(16)),
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};
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static const struct ccu_reset a80_mmc_resets[] = {
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[0] = GATE(0x0, BIT(18)),
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[1] = GATE(0x4, BIT(18)),
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[2] = GATE(0x8, BIT(18)),
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[3] = GATE(0xc, BIT(18)),
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};
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static const struct ccu_desc a80_ccu_desc = {
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.gates = a80_gates,
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.resets = a80_resets,
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};
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static const struct ccu_desc a80_mmc_clk_desc = {
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.gates = a80_mmc_gates,
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.resets = a80_mmc_resets,
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};
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static int a80_clk_bind(struct udevice *dev)
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{
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ulong count = ARRAY_SIZE(a80_resets);
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if (device_is_compatible(dev, "allwinner,sun9i-a80-mmc-config-clk"))
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count = ARRAY_SIZE(a80_mmc_resets);
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return sunxi_reset_bind(dev, count);
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}
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static const struct udevice_id a80_ccu_ids[] = {
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{ .compatible = "allwinner,sun9i-a80-ccu",
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.data = (ulong)&a80_ccu_desc },
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{ .compatible = "allwinner,sun9i-a80-mmc-config-clk",
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.data = (ulong)&a80_mmc_clk_desc },
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{ }
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};
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U_BOOT_DRIVER(clk_sun9i_a80) = {
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.name = "sun9i_a80_ccu",
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.id = UCLASS_CLK,
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.of_match = a80_ccu_ids,
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.priv_auto = sizeof(struct ccu_priv),
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.ops = &sunxi_clk_ops,
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.probe = sunxi_clk_probe,
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.bind = a80_clk_bind,
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};
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