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41575d8e4c
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
152 lines
3.6 KiB
C
152 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Allwinner LCD driver
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*
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* (C) Copyright 2017 Vasily Khoruzhick <anarsoul@gmail.com>
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*/
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#include <common.h>
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#include <display.h>
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#include <log.h>
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#include <video_bridge.h>
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#include <backlight.h>
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#include <dm.h>
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#include <edid.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/lcdc.h>
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#include <asm/arch/gpio.h>
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#include <asm/gpio.h>
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struct sunxi_lcd_priv {
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struct display_timing timing;
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int panel_bpp;
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};
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static void sunxi_lcdc_config_pinmux(void)
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{
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#ifdef CONFIG_MACH_SUN50I
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int pin;
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for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(21); pin++) {
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sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0);
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sunxi_gpio_set_drv(pin, 3);
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}
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#endif
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}
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static int sunxi_lcd_enable(struct udevice *dev, int bpp,
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const struct display_timing *edid)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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struct sunxi_lcdc_reg * const lcdc =
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(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
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struct sunxi_lcd_priv *priv = dev_get_priv(dev);
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struct udevice *backlight;
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int clk_div, clk_double, ret;
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/* Reset off */
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setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
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/* Clock on */
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setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
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lcdc_init(lcdc);
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sunxi_lcdc_config_pinmux();
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lcdc_pll_set(ccm, 0, edid->pixelclock.typ / 1000,
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&clk_div, &clk_double, false);
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lcdc_tcon0_mode_set(lcdc, edid, clk_div, false,
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priv->panel_bpp, CONFIG_VIDEO_LCD_DCLK_PHASE);
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lcdc_enable(lcdc, priv->panel_bpp);
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ret = uclass_get_device(UCLASS_PANEL_BACKLIGHT, 0, &backlight);
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if (!ret)
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backlight_enable(backlight);
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return 0;
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}
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static int sunxi_lcd_read_timing(struct udevice *dev,
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struct display_timing *timing)
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{
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struct sunxi_lcd_priv *priv = dev_get_priv(dev);
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memcpy(timing, &priv->timing, sizeof(struct display_timing));
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return 0;
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}
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static int sunxi_lcd_probe(struct udevice *dev)
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{
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struct udevice *cdev;
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struct sunxi_lcd_priv *priv = dev_get_priv(dev);
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int ret;
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int node, timing_node, val;
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#ifdef CONFIG_VIDEO_BRIDGE
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/* Try to get timings from bridge first */
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ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &cdev);
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if (!ret) {
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u8 edid[EDID_SIZE];
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int channel_bpp;
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ret = video_bridge_attach(cdev);
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if (ret) {
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debug("video bridge attach failed: %d\n", ret);
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return ret;
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}
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ret = video_bridge_read_edid(cdev, edid, EDID_SIZE);
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if (ret > 0) {
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ret = edid_get_timing(edid, ret,
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&priv->timing, &channel_bpp);
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priv->panel_bpp = channel_bpp * 3;
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if (!ret)
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return ret;
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}
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}
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#endif
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/* Fallback to timings from DT if there's no bridge or
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* if reading EDID failed
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*/
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ret = uclass_get_device(UCLASS_PANEL, 0, &cdev);
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if (ret) {
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debug("video panel not found: %d\n", ret);
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return ret;
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}
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if (fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(cdev),
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0, &priv->timing)) {
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debug("%s: Failed to decode display timing\n", __func__);
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return -EINVAL;
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}
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timing_node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(cdev),
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"display-timings");
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node = fdt_first_subnode(gd->fdt_blob, timing_node);
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val = fdtdec_get_int(gd->fdt_blob, node, "bits-per-pixel", -1);
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if (val != -1)
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priv->panel_bpp = val;
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else
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priv->panel_bpp = 18;
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return 0;
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}
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static const struct dm_display_ops sunxi_lcd_ops = {
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.read_timing = sunxi_lcd_read_timing,
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.enable = sunxi_lcd_enable,
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};
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U_BOOT_DRIVER(sunxi_lcd) = {
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.name = "sunxi_lcd",
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.id = UCLASS_DISPLAY,
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.ops = &sunxi_lcd_ops,
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.probe = sunxi_lcd_probe,
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.priv_auto = sizeof(struct sunxi_lcd_priv),
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};
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#ifdef CONFIG_MACH_SUN50I
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U_BOOT_DEVICE(sunxi_lcd) = {
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.name = "sunxi_lcd"
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};
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#endif
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