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41575d8e4c
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
425 lines
10 KiB
C
425 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Vasily Khoruzhick <anarsoul@gmail.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <i2c.h>
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#include <edid.h>
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#include <log.h>
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#include <video_bridge.h>
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#include <linux/delay.h>
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#include "../anx98xx-edp.h"
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#define DP_MAX_LINK_RATE 0x001
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#define DP_MAX_LANE_COUNT 0x002
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#define DP_MAX_LANE_COUNT_MASK 0x1f
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struct anx6345_priv {
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u8 edid[EDID_SIZE];
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};
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static int anx6345_write(struct udevice *dev, unsigned int addr_off,
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unsigned char reg_addr, unsigned char value)
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{
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uint8_t buf[2];
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struct i2c_msg msg;
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int ret;
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msg.addr = addr_off;
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msg.flags = 0;
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buf[0] = reg_addr;
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buf[1] = value;
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msg.buf = buf;
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msg.len = 2;
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ret = dm_i2c_xfer(dev, &msg, 1);
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if (ret) {
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debug("%s: write failed, reg=%#x, value=%#x, ret=%d\n",
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__func__, reg_addr, value, ret);
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return ret;
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}
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return 0;
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}
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static int anx6345_read(struct udevice *dev, unsigned int addr_off,
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unsigned char reg_addr, unsigned char *value)
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{
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uint8_t addr, val;
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struct i2c_msg msg[2];
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int ret;
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msg[0].addr = addr_off;
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msg[0].flags = 0;
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addr = reg_addr;
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msg[0].buf = &addr;
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msg[0].len = 1;
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msg[1].addr = addr_off;
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msg[1].flags = I2C_M_RD;
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msg[1].buf = &val;
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msg[1].len = 1;
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ret = dm_i2c_xfer(dev, msg, 2);
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if (ret) {
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debug("%s: read failed, reg=%.2x, value=%p, ret=%d\n",
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__func__, (int)reg_addr, value, ret);
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return ret;
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}
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*value = val;
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return 0;
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}
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static int anx6345_write_r0(struct udevice *dev, unsigned char reg_addr,
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unsigned char value)
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{
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struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
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return anx6345_write(dev, chip->chip_addr, reg_addr, value);
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}
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static int anx6345_read_r0(struct udevice *dev, unsigned char reg_addr,
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unsigned char *value)
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{
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struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
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return anx6345_read(dev, chip->chip_addr, reg_addr, value);
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}
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static int anx6345_write_r1(struct udevice *dev, unsigned char reg_addr,
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unsigned char value)
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{
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struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
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return anx6345_write(dev, chip->chip_addr + 1, reg_addr, value);
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}
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static int anx6345_read_r1(struct udevice *dev, unsigned char reg_addr,
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unsigned char *value)
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{
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struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
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return anx6345_read(dev, chip->chip_addr + 1, reg_addr, value);
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}
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static int anx6345_set_backlight(struct udevice *dev, int percent)
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{
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return -ENOSYS;
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}
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static int anx6345_aux_wait(struct udevice *dev)
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{
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int ret = -ETIMEDOUT;
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u8 v;
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int retries = 1000;
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do {
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anx6345_read_r0(dev, ANX9804_DP_AUX_CH_CTL_2, &v);
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if (!(v & ANX9804_AUX_EN)) {
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ret = 0;
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break;
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}
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udelay(100);
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} while (retries--);
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if (ret) {
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debug("%s: timed out waiting for AUX_EN to clear\n", __func__);
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return ret;
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}
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ret = -ETIMEDOUT;
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retries = 1000;
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do {
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anx6345_read_r1(dev, ANX9804_DP_INT_STA, &v);
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if (v & ANX9804_RPLY_RECEIV) {
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ret = 0;
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break;
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}
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udelay(100);
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} while (retries--);
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if (ret) {
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debug("%s: timed out waiting to receive reply\n", __func__);
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return ret;
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}
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/* Clear RPLY_RECEIV bit */
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anx6345_write_r1(dev, ANX9804_DP_INT_STA, v);
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anx6345_read_r0(dev, ANX9804_AUX_CH_STA, &v);
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if ((v & ANX9804_AUX_STATUS_MASK) != 0) {
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debug("AUX status: %d\n", v & ANX9804_AUX_STATUS_MASK);
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ret = -EIO;
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}
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return ret;
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}
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static void anx6345_aux_addr(struct udevice *dev, u32 addr)
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{
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u8 val;
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val = addr & 0xff;
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anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_7_0, val);
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val = (addr >> 8) & 0xff;
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anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_15_8, val);
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val = (addr >> 16) & 0x0f;
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anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_19_16, val);
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}
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static int anx6345_aux_transfer(struct udevice *dev, u8 req,
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u32 addr, u8 *buf, size_t len)
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{
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int i, ret;
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u8 ctrl1 = req;
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u8 ctrl2 = ANX9804_AUX_EN;
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if (len > 16)
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return -E2BIG;
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if (len)
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ctrl1 |= ANX9804_AUX_LENGTH(len);
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else
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ctrl2 |= ANX9804_ADDR_ONLY;
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if (len && !(req & ANX9804_AUX_TX_COMM_READ)) {
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for (i = 0; i < len; i++)
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anx6345_write_r0(dev, ANX9804_BUF_DATA_0 + i, buf[i]);
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}
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anx6345_aux_addr(dev, addr);
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anx6345_write_r0(dev, ANX9804_DP_AUX_CH_CTL_1, ctrl1);
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anx6345_write_r0(dev, ANX9804_DP_AUX_CH_CTL_2, ctrl2);
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ret = anx6345_aux_wait(dev);
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if (ret) {
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debug("AUX transaction timed out\n");
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return ret;
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}
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if (len && (req & ANX9804_AUX_TX_COMM_READ)) {
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for (i = 0; i < len; i++)
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anx6345_read_r0(dev, ANX9804_BUF_DATA_0 + i, &buf[i]);
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}
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return 0;
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}
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static int anx6345_read_aux_i2c(struct udevice *dev, u8 chip_addr,
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u8 offset, size_t count, u8 *buf)
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{
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int i, ret;
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size_t cur_cnt;
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u8 cur_offset;
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for (i = 0; i < count; i += 16) {
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cur_cnt = (count - i) > 16 ? 16 : count - i;
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cur_offset = offset + i;
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ret = anx6345_aux_transfer(dev, ANX9804_AUX_TX_COMM_MOT,
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chip_addr, &cur_offset, 1);
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if (ret) {
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debug("%s: failed to set i2c offset: %d\n",
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__func__, ret);
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return ret;
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}
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ret = anx6345_aux_transfer(dev, ANX9804_AUX_TX_COMM_READ,
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chip_addr, buf + i, cur_cnt);
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if (ret) {
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debug("%s: failed to read from i2c device: %d\n",
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__func__, ret);
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return ret;
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}
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}
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return 0;
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}
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static int anx6345_read_dpcd(struct udevice *dev, u32 reg, u8 *val)
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{
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int ret;
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ret = anx6345_aux_transfer(dev,
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ANX9804_AUX_TX_COMM_READ |
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ANX9804_AUX_TX_COMM_DP_TRANSACTION,
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reg, val, 1);
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if (ret) {
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debug("Failed to read DPCD\n");
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return ret;
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}
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return 0;
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}
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static int anx6345_read_edid(struct udevice *dev, u8 *buf, int size)
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{
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struct anx6345_priv *priv = dev_get_priv(dev);
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if (size > EDID_SIZE)
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size = EDID_SIZE;
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memcpy(buf, priv->edid, size);
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return size;
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}
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static int anx6345_attach(struct udevice *dev)
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{
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/* No-op */
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return 0;
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}
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static int anx6345_enable(struct udevice *dev)
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{
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u8 chipid, colordepth, lanes, data_rate, c;
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int ret, i, bpp;
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struct display_timing timing;
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struct anx6345_priv *priv = dev_get_priv(dev);
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/* Deassert reset and enable power */
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ret = video_bridge_set_active(dev, true);
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if (ret)
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return ret;
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/* Reset */
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anx6345_write_r1(dev, ANX9804_RST_CTRL_REG, 1);
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mdelay(100);
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anx6345_write_r1(dev, ANX9804_RST_CTRL_REG, 0);
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/* Write 0 to the powerdown reg (powerup everything) */
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anx6345_write_r1(dev, ANX9804_POWERD_CTRL_REG, 0);
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ret = anx6345_read_r1(dev, ANX9804_DEV_IDH_REG, &chipid);
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if (ret)
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debug("%s: read id failed: %d\n", __func__, ret);
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switch (chipid) {
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case 0x63:
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debug("ANX63xx detected.\n");
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break;
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default:
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debug("Error anx6345 chipid mismatch: %.2x\n", (int)chipid);
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return -ENODEV;
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}
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for (i = 0; i < 100; i++) {
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anx6345_read_r0(dev, ANX9804_SYS_CTRL2_REG, &c);
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anx6345_write_r0(dev, ANX9804_SYS_CTRL2_REG, c);
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anx6345_read_r0(dev, ANX9804_SYS_CTRL2_REG, &c);
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if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0)
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break;
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mdelay(5);
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}
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if (i == 100)
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debug("Error anx6345 clock is not stable\n");
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/* Set a bunch of analog related register values */
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anx6345_write_r0(dev, ANX9804_PLL_CTRL_REG, 0x00);
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anx6345_write_r1(dev, ANX9804_ANALOG_DEBUG_REG1, 0x70);
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anx6345_write_r0(dev, ANX9804_LINK_DEBUG_REG, 0x30);
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/* Force HPD */
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anx6345_write_r0(dev, ANX9804_SYS_CTRL3_REG,
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ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);
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/* Power up and configure lanes */
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anx6345_write_r0(dev, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
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anx6345_write_r0(dev, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
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anx6345_write_r0(dev, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
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anx6345_write_r0(dev, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
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anx6345_write_r0(dev, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
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/* Reset AUX CH */
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anx6345_write_r1(dev, ANX9804_RST_CTRL2_REG,
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ANX9804_RST_CTRL2_AUX);
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anx6345_write_r1(dev, ANX9804_RST_CTRL2_REG, 0);
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/* Powerdown audio and some other unused bits */
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anx6345_write_r1(dev, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
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anx6345_write_r0(dev, ANX9804_HDCP_CONTROL_0_REG, 0x00);
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anx6345_write_r0(dev, 0xa7, 0x00);
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anx6345_read_aux_i2c(dev, 0x50, 0x0, EDID_SIZE, priv->edid);
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if (edid_get_timing(priv->edid, EDID_SIZE, &timing, &bpp) != 0) {
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debug("Failed to parse EDID\n");
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return -EIO;
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}
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debug("%s: panel found: %dx%d, bpp %d\n", __func__,
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timing.hactive.typ, timing.vactive.typ, bpp);
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if (bpp == 6)
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colordepth = 0x00; /* 6 bit */
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else
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colordepth = 0x10; /* 8 bit */
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anx6345_write_r1(dev, ANX9804_VID_CTRL2_REG, colordepth);
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if (anx6345_read_dpcd(dev, DP_MAX_LINK_RATE, &data_rate)) {
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debug("%s: Failed to DP_MAX_LINK_RATE\n", __func__);
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return -EIO;
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}
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debug("%s: data_rate: %d\n", __func__, (int)data_rate);
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if (anx6345_read_dpcd(dev, DP_MAX_LANE_COUNT, &lanes)) {
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debug("%s: Failed to read DP_MAX_LANE_COUNT\n", __func__);
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return -EIO;
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}
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lanes &= DP_MAX_LANE_COUNT_MASK;
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debug("%s: lanes: %d\n", __func__, (int)lanes);
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/* Set data-rate / lanes */
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anx6345_write_r0(dev, ANX9804_LINK_BW_SET_REG, data_rate);
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anx6345_write_r0(dev, ANX9804_LANE_COUNT_SET_REG, lanes);
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/* Link training */
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anx6345_write_r0(dev, ANX9804_LINK_TRAINING_CTRL_REG,
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ANX9804_LINK_TRAINING_CTRL_EN);
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mdelay(5);
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for (i = 0; i < 100; i++) {
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anx6345_read_r0(dev, ANX9804_LINK_TRAINING_CTRL_REG, &c);
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if ((chipid == 0x63) && (c & 0x80) == 0)
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break;
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mdelay(5);
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}
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if (i == 100) {
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debug("Error anx6345 link training timeout\n");
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return -ENODEV;
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}
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/* Enable */
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anx6345_write_r1(dev, ANX9804_VID_CTRL1_REG,
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ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
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/* Force stream valid */
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anx6345_write_r0(dev, ANX9804_SYS_CTRL3_REG,
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ANX9804_SYS_CTRL3_F_HPD |
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ANX9804_SYS_CTRL3_HPD_CTRL |
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ANX9804_SYS_CTRL3_F_VALID |
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ANX9804_SYS_CTRL3_VALID_CTRL);
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return 0;
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}
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static int anx6345_probe(struct udevice *dev)
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{
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if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
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return -EPROTONOSUPPORT;
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return anx6345_enable(dev);
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}
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struct video_bridge_ops anx6345_ops = {
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.attach = anx6345_attach,
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.set_backlight = anx6345_set_backlight,
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.read_edid = anx6345_read_edid,
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};
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static const struct udevice_id anx6345_ids[] = {
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{ .compatible = "analogix,anx6345", },
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{ }
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};
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U_BOOT_DRIVER(analogix_anx6345) = {
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.name = "analogix_anx6345",
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.id = UCLASS_VIDEO_BRIDGE,
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.of_match = anx6345_ids,
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.probe = anx6345_probe,
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.ops = &anx6345_ops,
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.priv_auto = sizeof(struct anx6345_priv),
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};
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