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41575d8e4c
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
390 lines
10 KiB
C
390 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Take linux kernel driver drivers/gpio/gpio-pca953x.c for reference.
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*
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* Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
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*
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*/
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/*
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* Note:
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* The driver's compatible table is borrowed from Linux Kernel,
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* but now max supported gpio pins is 24 and only PCA953X_TYPE
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* is supported. PCA957X_TYPE is not supported now.
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* Also the Polarity Inversion feature is not supported now.
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*
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* TODO:
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* 1. Support PCA957X_TYPE
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* 2. Support Polarity Inversion
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*/
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#include <common.h>
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#include <errno.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <i2c.h>
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#include <malloc.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <linux/bitops.h>
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#define PCA953X_INPUT 0
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#define PCA953X_OUTPUT 1
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#define PCA953X_INVERT 2
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#define PCA953X_DIRECTION 3
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#define PCA_GPIO_MASK 0x00FF
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#define PCA_INT 0x0100
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#define PCA953X_TYPE 0x1000
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#define PCA957X_TYPE 0x2000
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#define PCA_TYPE_MASK 0xF000
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#define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
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enum {
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PCA953X_DIRECTION_IN,
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PCA953X_DIRECTION_OUT,
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};
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#define MAX_BANK 5
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#define BANK_SZ 8
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/*
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* struct pca953x_info - Data for pca953x
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*
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* @dev: udevice structure for the device
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* @addr: i2c slave address
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* @invert: Polarity inversion or not
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* @gpio_count: the number of gpio pins that the device supports
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* @chip_type: indicate the chip type,PCA953X or PCA957X
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* @bank_count: the number of banks that the device supports
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* @reg_output: array to hold the value of output registers
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* @reg_direction: array to hold the value of direction registers
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*/
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struct pca953x_info {
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struct udevice *dev;
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int addr;
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int invert;
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int gpio_count;
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int chip_type;
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int bank_count;
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u8 reg_output[MAX_BANK];
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u8 reg_direction[MAX_BANK];
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};
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static int pca953x_write_single(struct udevice *dev, int reg, u8 val,
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int offset)
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{
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struct pca953x_info *info = dev_get_platdata(dev);
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int bank_shift = fls((info->gpio_count - 1) / BANK_SZ);
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int off = offset / BANK_SZ;
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int ret = 0;
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ret = dm_i2c_write(dev, (reg << bank_shift) + off, &val, 1);
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if (ret) {
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dev_err(dev, "%s error\n", __func__);
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return ret;
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}
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return 0;
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}
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static int pca953x_read_single(struct udevice *dev, int reg, u8 *val,
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int offset)
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{
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struct pca953x_info *info = dev_get_platdata(dev);
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int bank_shift = fls((info->gpio_count - 1) / BANK_SZ);
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int off = offset / BANK_SZ;
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int ret;
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u8 byte;
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ret = dm_i2c_read(dev, (reg << bank_shift) + off, &byte, 1);
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if (ret) {
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dev_err(dev, "%s error\n", __func__);
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return ret;
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}
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*val = byte;
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return 0;
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}
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static int pca953x_read_regs(struct udevice *dev, int reg, u8 *val)
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{
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struct pca953x_info *info = dev_get_platdata(dev);
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int ret = 0;
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if (info->gpio_count <= 8) {
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ret = dm_i2c_read(dev, reg, val, 1);
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} else if (info->gpio_count <= 16) {
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ret = dm_i2c_read(dev, reg << 1, val, info->bank_count);
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} else if (info->gpio_count <= 24) {
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/* Auto increment */
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ret = dm_i2c_read(dev, (reg << 2) | 0x80, val,
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info->bank_count);
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} else if (info->gpio_count == 40) {
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/* Auto increment */
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ret = dm_i2c_read(dev, (reg << 3) | 0x80, val,
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info->bank_count);
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} else {
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dev_err(dev, "Unsupported now\n");
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return -EINVAL;
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}
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return ret;
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}
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static int pca953x_write_regs(struct udevice *dev, int reg, u8 *val)
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{
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struct pca953x_info *info = dev_get_platdata(dev);
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int ret = 0;
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if (info->gpio_count <= 8) {
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ret = dm_i2c_write(dev, reg, val, 1);
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} else if (info->gpio_count <= 16) {
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ret = dm_i2c_write(dev, reg << 1, val, info->bank_count);
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} else if (info->gpio_count <= 24) {
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/* Auto increment */
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ret = dm_i2c_write(dev, (reg << 2) | 0x80, val,
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info->bank_count);
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} else if (info->gpio_count == 40) {
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/* Auto increment */
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ret = dm_i2c_write(dev, (reg << 3) | 0x80, val, info->bank_count);
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} else {
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return -EINVAL;
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}
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return ret;
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}
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static int pca953x_is_output(struct udevice *dev, int offset)
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{
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struct pca953x_info *info = dev_get_platdata(dev);
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int bank = offset / BANK_SZ;
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int off = offset % BANK_SZ;
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/*0: output; 1: input */
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return !(info->reg_direction[bank] & (1 << off));
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}
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static int pca953x_get_value(struct udevice *dev, uint offset)
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{
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int ret;
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u8 val = 0;
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int off = offset % BANK_SZ;
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ret = pca953x_read_single(dev, PCA953X_INPUT, &val, offset);
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if (ret)
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return ret;
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return (val >> off) & 0x1;
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}
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static int pca953x_set_value(struct udevice *dev, uint offset, int value)
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{
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struct pca953x_info *info = dev_get_platdata(dev);
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int bank = offset / BANK_SZ;
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int off = offset % BANK_SZ;
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u8 val;
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int ret;
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if (value)
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val = info->reg_output[bank] | (1 << off);
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else
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val = info->reg_output[bank] & ~(1 << off);
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ret = pca953x_write_single(dev, PCA953X_OUTPUT, val, offset);
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if (ret)
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return ret;
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info->reg_output[bank] = val;
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return 0;
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}
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static int pca953x_set_direction(struct udevice *dev, uint offset, int dir)
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{
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struct pca953x_info *info = dev_get_platdata(dev);
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int bank = offset / BANK_SZ;
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int off = offset % BANK_SZ;
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u8 val;
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int ret;
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if (dir == PCA953X_DIRECTION_IN)
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val = info->reg_direction[bank] | (1 << off);
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else
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val = info->reg_direction[bank] & ~(1 << off);
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ret = pca953x_write_single(dev, PCA953X_DIRECTION, val, offset);
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if (ret)
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return ret;
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info->reg_direction[bank] = val;
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return 0;
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}
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static int pca953x_direction_input(struct udevice *dev, uint offset)
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{
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return pca953x_set_direction(dev, offset, PCA953X_DIRECTION_IN);
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}
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static int pca953x_direction_output(struct udevice *dev, uint offset, int value)
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{
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/* Configure output value. */
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pca953x_set_value(dev, offset, value);
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/* Configure direction as output. */
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pca953x_set_direction(dev, offset, PCA953X_DIRECTION_OUT);
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return 0;
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}
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static int pca953x_get_function(struct udevice *dev, uint offset)
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{
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if (pca953x_is_output(dev, offset))
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return GPIOF_OUTPUT;
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else
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return GPIOF_INPUT;
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}
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static int pca953x_xlate(struct udevice *dev, struct gpio_desc *desc,
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struct ofnode_phandle_args *args)
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{
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desc->offset = args->args[0];
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desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
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return 0;
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}
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static const struct dm_gpio_ops pca953x_ops = {
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.direction_input = pca953x_direction_input,
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.direction_output = pca953x_direction_output,
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.get_value = pca953x_get_value,
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.set_value = pca953x_set_value,
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.get_function = pca953x_get_function,
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.xlate = pca953x_xlate,
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};
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static int pca953x_probe(struct udevice *dev)
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{
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struct pca953x_info *info = dev_get_platdata(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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char name[32], label[8], *str;
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int addr;
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ulong driver_data;
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int ret;
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int size;
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const u8 *tmp;
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u8 val[MAX_BANK];
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addr = dev_read_addr(dev);
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if (addr == 0)
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return -ENODEV;
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info->addr = addr;
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driver_data = dev_get_driver_data(dev);
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info->gpio_count = driver_data & PCA_GPIO_MASK;
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if (info->gpio_count > MAX_BANK * BANK_SZ) {
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dev_err(dev, "Max support %d pins now\n", MAX_BANK * BANK_SZ);
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return -EINVAL;
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}
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info->chip_type = PCA_CHIP_TYPE(driver_data);
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if (info->chip_type != PCA953X_TYPE) {
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dev_err(dev, "Only support PCA953X chip type now.\n");
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return -EINVAL;
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}
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info->bank_count = DIV_ROUND_UP(info->gpio_count, BANK_SZ);
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ret = pca953x_read_regs(dev, PCA953X_OUTPUT, info->reg_output);
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if (ret) {
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dev_err(dev, "Error reading output register\n");
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return ret;
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}
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ret = pca953x_read_regs(dev, PCA953X_DIRECTION, info->reg_direction);
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if (ret) {
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dev_err(dev, "Error reading direction register\n");
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return ret;
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}
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tmp = dev_read_prop(dev, "label", &size);
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if (tmp) {
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memcpy(label, tmp, sizeof(label) - 1);
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label[sizeof(label) - 1] = '\0';
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snprintf(name, sizeof(name), "%s@%x_", label, info->addr);
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} else {
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snprintf(name, sizeof(name), "gpio@%x_", info->addr);
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}
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/* Clear the polarity registers to no invert */
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memset(val, 0, MAX_BANK);
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ret = pca953x_write_regs(dev, PCA953X_INVERT, val);
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if (ret < 0) {
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dev_err(dev, "Error writing invert register\n");
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return ret;
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}
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str = strdup(name);
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if (!str)
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return -ENOMEM;
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uc_priv->bank_name = str;
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uc_priv->gpio_count = info->gpio_count;
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dev_dbg(dev, "%s is ready\n", str);
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return 0;
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}
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#define OF_953X(__nrgpio, __int) (ulong)(__nrgpio | PCA953X_TYPE | __int)
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#define OF_957X(__nrgpio, __int) (ulong)(__nrgpio | PCA957X_TYPE | __int)
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static const struct udevice_id pca953x_ids[] = {
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{ .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
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{ .compatible = "nxp,pca9534", .data = OF_953X(8, PCA_INT), },
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{ .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
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{ .compatible = "nxp,pca9536", .data = OF_953X(4, 0), },
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{ .compatible = "nxp,pca9537", .data = OF_953X(4, PCA_INT), },
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{ .compatible = "nxp,pca9538", .data = OF_953X(8, PCA_INT), },
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{ .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
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{ .compatible = "nxp,pca9554", .data = OF_953X(8, PCA_INT), },
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{ .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
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{ .compatible = "nxp,pca9556", .data = OF_953X(8, 0), },
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{ .compatible = "nxp,pca9557", .data = OF_953X(8, 0), },
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{ .compatible = "nxp,pca9574", .data = OF_957X(8, PCA_INT), },
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{ .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
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{ .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
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{ .compatible = "maxim,max7310", .data = OF_953X(8, 0), },
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{ .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
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{ .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
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{ .compatible = "maxim,max7315", .data = OF_953X(8, PCA_INT), },
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{ .compatible = "ti,pca6107", .data = OF_953X(8, PCA_INT), },
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{ .compatible = "ti,tca6408", .data = OF_953X(8, PCA_INT), },
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{ .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
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{ .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
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{ .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), },
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{ .compatible = "onsemi,pca9654", .data = OF_953X(8, PCA_INT), },
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{ .compatible = "exar,xra1202", .data = OF_953X(8, 0), },
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{ }
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};
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U_BOOT_DRIVER(pca953x) = {
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.name = "pca953x",
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.id = UCLASS_GPIO,
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.ops = &pca953x_ops,
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.probe = pca953x_probe,
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.platdata_auto = sizeof(struct pca953x_info),
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.of_match = pca953x_ids,
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};
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