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Trent Piepho a5d212a263 mpc8xxx: LCRR[CLKDIV] is sometimes five bits 
On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits
instead of four.

In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems.  It
should be safe as the fifth bit was defined as reserved and set to 0.

Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-19 18:20:25 -06:00
..
config.mk mpc85xx: Add support for SBC8548 (updated) 2008-01-09 16:25:03 -06:00
ddr.c Pass dimm parameters to populate populate controller options 2008-10-18 21:54:04 +02:00
law.c rename CFG_ macros to CONFIG_SYS 2008-10-18 21:54:03 +02:00
Makefile FSL DDR: Convert sbc8548 to new DDR code. 2008-08-27 11:43:51 -05:00
sbc8548.c mpc8xxx: LCRR[CLKDIV] is sometimes five bits 2008-12-19 18:20:25 -06:00
tlb.c rename CFG_ macros to CONFIG_SYS 2008-10-18 21:54:03 +02:00
u-boot.lds Align end of bss by 4 bytes 2008-11-18 23:13:16 +01:00